Pipelined FFT processor with memory address interleaving

Details Pipelined FFT processor with memory address interleaving Pipelined FFT processor with memory address interleaving

2004-05-13

2008-09-23

Mai, Tan V. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S404000

Reexamination Certificate

active

07428564

ABSTRACT:
A fast Fourier transform processor using a single delay path and a permuter provides a reduction in the implementation area and a related reduction in power consumption through efficiencies obtained by the modification of a butterfly unit and the use of a novel interleaver. The modified butterfly unit is obtained by the removal of complex variable multipliers, which is possible due to the simplification of twiddle factors in the stages that correspond to the modified butterfly unit.

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