Pipelined fast fourier transform processor

Details Pipelined fast fourier transform processor Pipelined fast fourier transform processor

1990-08-10

1991-08-06

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 15332

Patent

active

050383116

ABSTRACT:
A pipeline Fast Fourier Transform arrangement includes a cascade of four Butterfly Arithmetic Units (BAU). Weighting and control signals are coupled to each BAU in the cascade. A multiplexed memory arrangement operated in a "ping-pong" manner stores four-stage partial FFT signal as it is generated, and returns it to the first BAU in the cascade for subsequent passes to generate multiple-stage FFT signals. Each BAU includes local memories cyclically fed and addressed to generate temporal offsets, which differ among the processors of the cascade.

REFERENCES:
patent: 3816729 (1974-06-01), Works
patent: 4275452 (1981-06-01), White
patent: 4899301 (1990-02-01), Nishitani et al.
patent: 4970674 (1990-11-01), White
"A guided tour of the fast Fourier transform" by Bergland, published at pp. 41-51 of the IEEE Spectrum, Jul. 1969.
"A Pipeline Fast Fourier Transform", By Groginsky et al., published at pp. 22-29 of Eascon '69 Record, 1969.
"Implementation of a Pipeline FET" by Sheats et al., published at pp. 156-157 of Nerem '70 record, 1970.
A paper entitled "FAST FOURIER TRANSFORM" pp. 149-154 by Sheats as Chapter 9, Radar Technology, Eli Brockner, Artech House Massachusetts 1977.

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