Pipelined error detection and correction apparatus with programm

Details Pipelined error detection and correction apparatus with programm Pipelined error detection and correction apparatus with programm

1987-06-09

1990-02-27

Smith, Jerry

Excavating

G06F 1110

Patent

active

049052420

ABSTRACT:
An error detection and correction apparatus utilizing seven internally generated check bits which are applied to incoming data signals on the next clock. The combination data signals are written into the system random access memory and are reapplied to the error detection and correction apparatus. An address trap register is programmed to trap the address of the single or multiple bit errors. The address trap register also captures the error flags and the syndrome bit so that detected faults can be isolated. A single bit error correction circuit is utilized to correct single bit errors in the data signal.

REFERENCES:
patent: 3644902 (1972-02-01), Beausoleil
patent: 4319356 (1982-03-01), Kocol
patent: 4335459 (1982-06-01), Miller
patent: 4371930 (1983-02-01), Kim
patent: 4488298 (1984-12-01), Bond et al.
patent: 4535455 (1985-08-01), Peterson
patent: 4646303 (1987-02-01), Narusawa
patent: 4646304 (1987-02-01), Fossati
Advanced Micro Devices, The AM2900 Familt Data Book with Related Support Circuits, Copyright 1979 b Advanced Micro Devices, Inc. pp. 2-312--2-328.

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