Pipelined error checking and correction for cache memories

Details Pipelined error checking and correction for cache memories Pipelined error checking and correction for cache memories

1989-09-19

1991-10-15

Smith, Jerry

Excavating

371 401, 371 381, H03M 1300

Patent

active

050581163

ABSTRACT:
A single error correction, double error detection function for cache memories does not affect the normal cache access time the addition of the ECC function. Check bits are provided for multiple bytes of data, thereby lowering the overhead of the error detecting and correcting technique. When a single error is detected, a cycle is inserted by the control circuitry of the cache chip. At the same time, the clocks for the CPU are held high until released by the cache chip on the next cycle. Error correction on multi-byte data is performed using the 72/64 Hamming code. The technique requires a 2-port cache array (one write port, and one read port). However, the density of a true 2-port array is too low; therefore, the technique is implemented with a 1-port array using a time multiplexing technique, providing an effective 2-port array but with the density of a single port array.

REFERENCES:
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patent: 4672614 (1987-06-01), Yoshida
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patent: 4748627 (1988-05-01), Ohsawa
patent: 4920539 (1990-04-01), Albonesi
patent: 4953164 (1990-08-01), Asakura et al.

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