Image analysis – Image compression or coding – Transform coding
Reexamination Certificate
1998-12-31
2003-06-10
Johnson, Timothy M. (Department: 2625)
Image analysis
Image compression or coding
Transform coding
C382S251000, C708S402000
Reexamination Certificate
active
06577772
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a technique for realizing a discrete cosine transform (DCT) algorithm which compresses image data through dividing the image data into various frequency components by using a spatial correlation on a screen, and particularly to a low-power pipelined DCT apparatus which is fit with a low-power required mobile video terminal.
2. Description of the Prior Art
The conventional image compressing devices employ a DCT operator, which is widely used in the International Standard such as JPEG, MPEG, H.263 and so on, for processing an orthogonal transform on the given image. The conventional image compressing devices employing the DCT operator dissolve the image data into various frequency image components in the range from a DC value to a high frequency. The conventional image compressing devices then execute a quantization and a variable length coding for compressing the image data.
FIG. 1
shows the above conventional image compressing device. As shown in the figure, the device includes a DCT operator
13
for calculating DCT coefficients from an input image data and a quantizer
14
for quantizing the DCT coefficients. The device also includes an inverse quantizer
15
, an inverse DCT operator
16
, an adder
17
, a plurality of switching logic units
12
,
19
, and a subtracter
11
, all of which form a feedback line for the quantized DCT coefficients. The device additionally includes an image memory
18
for extracting a motion vector V. In addition, the device further includes a coding controller
10
for controlling the quantizer
14
and the switching logic units
12
,
19
.
In the figure, in the fact that the DCT operator
13
can process an image input data of N×N size, there exist various fast algorithms such as a butterfly structure based on a multiplier.
However, when realizing a DCT operator having the butterfly structure based on a multiplier with an integrated circuit (IC), there are disadvantages in speed and area, because it should carry a complex routing process and many multipliers, caused by an irregular algorithm structure.
In addition, there is a conventional method such as a distributed arithmetic operation for executing the DCT operation by substituting the multipliers with read only memories (ROM) and adders.
The conventional DCT operators, such as the butterfly structure DCT operator and the distributed arithmetic DCT operator as described above, have structures of calculating coefficients in all DCT regions regardless of characteristics of the input image data.
Now, a DCT process in the conventional image compressing device is explained. According to the DCT process, N
4
multiplications are operated between DCT kernels, obtained from a cosine function, and input N×N image data for acquiring N×N coefficients in the frequency domain as expressed in the equation
z
(
k
,
l
)
=
2
N
α
(
k
)
α
(
l
)
∑
m
=
0
N
-
1
∑
m
=
0
N
-
1
x
(
m
,
n
)
×
cos
(
2
m
+
1
)
π
k
2
N
cos
(
2
n
+
1
)
π
l
2
N
Equation
1
where x(m, n) is the input image data, z(k,l) is the DCT coefficient, and
α
(
0
)
=
1
2
,
α
(
k
)
=
1
(
k
≠
0
,
0
≤
m
,
n
,
k
,
i
<
N
)
However, when employing row-column decomposition in
FIG. 2
by using characteristics of the DCT kernel, the number of the multiplication operations can be decreased to 2N
3
.
In such row-column decomposition, after the input N×N image data passes through a one-dimensional DCT (1D DCT) operator
13
-
1
in rows, the result thereof is temporarily stored in a transposition memory
13
-
2
. Then, after reading the result in columns, a two-dimensional DCT (2D DCT) operation is executed through a 1D DCT operator
13
-
3
. Because the 1D DCT operator also employs various fast algorithms so that it enhances overall performance, the number of multipliers used in the whole DCT operation should be decreased.
In addition, because the multiplier can be substituted by the ROM and the adder in the distributed arithmetic operation, which allows easier inner product operation of a vector, that may be applied to the DCT operation.
However, though there are many standards in the International Standard for a digital image data compression now, which an inverse discrete cosine transform (IDCT) should meet in a receiving unit for recovering the image, no standard for DCT is specially referred to.
In the image data compressing process, energy is, however, mainly focused on low-frequency data among the data processed by the DCT operation. Then after the quantizing process, there remain only a few lower-frequency coefficients near DCT coefficients about a DC value to be coded, and remaining most higher-frequency coefficients are to be 0 and thrown out.
Therefore, in radio-oriented applications, such as the mobile video terminal, in the facts that a channel band width is restricted, a compression ratio of the image data is high, and low-power should be consumed, the complex calculation for all high-frequency components is not required in the DCT operation.
SUMMARY OF THE INVENTION
Therefore, the present invention is designed to solve the above problems, so object of the invention is to provide a pipelined DCT apparatus for having low complexity in a hardware configuration and consuming low power, so to be more suitable to a mobile video terminal.
In order to accomplish the above object, the present invention provides a DCT operating unit, in which a range of DCT coefficients for a calculation is controllable among an entire DCT region. The range of DCT coefficients for the calculation can be determined by an external control signal. The range of DCT coefficients for the calculation can be also determined by characteristics of input image data. The characteristics of the input image data might be estimated from statistical characteristics of previously calculated DCT coefficients.
In another embodiment, the present invention provides a 2D DCT device including a first 1D DCT operator for executing a 1D DCT operation in rows about input image data; a transposition memory for temporarily storing a result of the first 1D DCT operator; a second 1D DCT operator for executing a 1D DCT operation in columns about the resultant data processed by the 1D DCT operation in rows and stored in the transposition memory; and a timing control logic unit for controlling operation of the first and second 1D DCT operators and the transposition memory according to a DCT block size control signal given from outside.
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patent: 5241395 (1993-08-01), Chen
patent: 5333012 (1994-07-01), Singhal et al.
patent: 5734755 (1998-03-01), Ramchandran et al.
patent: 5739863 (1998-04-01), Ohtsuki
patent: 5892847 (1999-04-01), Johnson
patent: 5894430 (1999-04-01), Ohara
patent: 5933194 (1999-08-01), Kim et al.
patent: 6105114 (2000-08-01), Okkuno
patent: 6141455 (2000-10-01), Matsuzawa
patent: 6333949 (2001-12-01), Nakagawa et al.
Bayat Ali
Johnson Timothy M.
McKenna Long & Aldridge LLP
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