Boots – shoes – and leggings
Patent
1988-07-20
1991-04-09
Fleming, Michael R.
Boots, shoes, and leggings
3642318, 3642623, 364230, G06F 938
Patent
active
050069802
ABSTRACT:
A pipelined CPU employs separate microinstruction pipelines for the execution unit and memory management unit. Deadlocks can occur in a pipelined CPU when there is data dependency in two consecutive instructions. The later instruction may stall the pipeline if operands fetched by an earlier instruction are needed, but the earlier instruction is not producing the memory request for the operands because the pipeline is stalled; this results in a deadlock. Using separate micro-pipelines, the earlier instruction is advanced independently of the rest of the pipeline, in the case of a deadlock, so that the operands for the later instruction are provided and the deadlock is broken.
REFERENCES:
patent: 4236206 (1980-11-01), Strecker et al.
patent: 4586130 (1986-04-01), Butts, Jr. et al.
patent: 4709324 (1987-11-01), Kloker
patent: 4714991 (1987-12-01), Eaton
patent: 4750112 (1988-06-01), Jones et al.
patent: 4760519 (1988-07-01), Papworth et al.
patent: 4794527 (1988-12-01), Stewart et al.
patent: 4812970 (1989-03-01), Kitamura et al.
Mishra, "The VAX Microarchitecture",Digital Technical Journal, Feb. 1987, pp. 20-33.
Troiani et al, "The VAX 8600 I Box, A Pipelined Implementation of the VAX Architecture," Digital Technical Journal, Aug. 1985, pp. 24-42.
Brown, III John F.
Sanders Douglas E.
Uhler George M.
Chun Debra A.
Digital Equipment Corporation
Fleming Michael R.
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