Pipelined data processor that detects an illegal instruction by

Details Pipelined data processor that detects an illegal instruction by Pipelined data processor that detects an illegal instruction by

1991-05-13

1997-07-22

Ellis, Richard L.

G06F 900

Patent

active

056511221

ABSTRACT:
A pipelined data processor (10) has a control unit (14') that detects an illegal instruction as well as legal instruction opcodes. An opcode decoder (28) decodes instructions. In response to decoding an illegal instruction, opcode decoder (28) provides no output signal. In response to decoding a legal instruction, opcode decoder (28) provides one of a plurality of output signals. A ROM (27) provides a first output in response to receiving no output from the decoder (28), and provides one of a plurality of second outputs in response to receiving one of a plurality of output signals from decoder (28). The first output of the ROM (27) is a first microword of a routine for processing the illegal instruction. Each of the second outputs of the ROM (27) is a first microword of a routine for processing the legal instruction received from the decoder (28).

REFERENCES:
patent: 3675214 (1972-07-01), Ellis et al.
patent: 4167778 (1979-09-01), Sipple
patent: 4446517 (1984-05-01), Katsura et al.
patent: 4466055 (1984-08-01), Kinoshita et al.
patent: 4488228 (1984-12-01), Crudele et al.
patent: 4710866 (1987-12-01), Zolnowsky et al.
patent: 4864535 (1989-09-01), Rogers et al.
patent: 5046040 (1991-09-01), Miyoshi

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