Pipelined data processing device having improved hardware contro

Details Pipelined data processing device having improved hardware contro Pipelined data processing device having improved hardware contro

1996-01-16

1998-10-13

Pan, Daniel H.

395569, 39580007, G06F 9302, G06F 938

Patent

active

058225579

ABSTRACT:
An arithmetic operation unit for operating according to pipeline control and an instruction decoder for controlling the arithmetic operation unit by decoding an instruction, including a state retaining unit for retaining a state of the operation of the arithmetic operation unit, wherein the instruction decoder controls the execution of the arithmetic operation unit according to the information stored by the state retaining unit. A state is set when the decoder issues a signal for starting the arithmetic operation unit and the state is cleared when the decoder issues a signal for stopping the operation of the arithmetic operation unit. The arithmetic operation unit further comprises a unit for obtaining a maximum and a minimum value with a simple construction. A multiplier of the arithmetic operation unit comprises a unit for performing an addition of an exponential part of a multiplier and that of a multiplicand with a simple construction. The arithmetic operation unit further comprises a data packing and unpacking unit for packing and unpacking vector data. The data processing device is divided into several units and scan paths are divided into several paths corresponding to respective units.

REFERENCES:
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patent: 4720811 (1988-01-01), Yamaguchi
patent: 4752873 (1988-06-01), Shonai et al.
patent: 4785393 (1988-11-01), Chu et al.
patent: 4868414 (1989-09-01), Kanazawa
patent: 4918600 (1990-04-01), Harper, III et al.
patent: 4926370 (1990-05-01), Brown et al.
patent: 5119324 (1992-06-01), Ahsan

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