Pipelined CPU with instruction fetch, execution and write back s

Details Pipelined CPU with instruction fetch, execution and write back s Pipelined CPU with instruction fetch, execution and write back s

1997-11-07

1998-07-21

Shah, Alpesh M.

395376, G06F 1576

Patent

active

057846340

ABSTRACT:
An integrated circuit CPU is provided. The CPU has a program counter register; an instruction register; an instruction decoder connected directly to the instruction register; a register file responsive to control signals from the instruction decoder; an ALU operating upon data from the register file and generating results responsive to the control signals; and a result register that holds results while the results are written back to the register file. The CPU has only three pipelined stages of operation. The three stages comprise fetching an instruction from the memory subsystem into the instruction register; executing an instruction in the instruction register; and writing back results in the result register to the register file. Operating speeds are comparable to CPUs with a greater number of stages.

REFERENCES:
patent: 5450555 (1995-09-01), Brown, III et al.
patent: 5461715 (1995-10-01), Matsuo et al.
patent: 5497355 (1996-03-01), Mills et al.
patent: 5553256 (1996-09-01), Fetterman et al.

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