Pipelined computer with control of instruction advance

Details Pipelined computer with control of instruction advance Pipelined computer with control of instruction advance

1993-07-12

1995-06-27

Lall, Parshotam S.

Boots, shoes, and leggings

364DIG1, G06F 938

Patent

active

054287561

ABSTRACT:
An instruction is fed to first and second pipelines at a same time. The instruction is advanced in the first pipeline. In addition, the instruction is advanced in the second pipeline. Advance of the instruction in the second pipeline is controlled in accordance with a position of the instruction in the first pipeline to synchronize advance of the instruction in the first pipeline and advance of the instruction in the second pipeline.

REFERENCES:
patent: 4270181 (1981-05-01), Tanakura et al.
patent: 4594655 (1986-06-01), Hao et al.
patent: 4750112 (1988-06-01), Jones et al.
patent: 4916652 (1990-04-01), Schwarz et al.
patent: 5006980 (1991-04-01), Sanders et al.
patent: 5193158 (1993-03-01), Kinney et al.
Microprocessing and Microprogramming. vol. 24, No. 1/5, Aug. 1988, Amsterdam NL, pp. 695-700, V. G. Oklobdzija `Issues in CPU--Coprocessor Communication and synchronisation`.

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