Pipelined compressor circuit

Details Pipelined compressor circuit Pipelined compressor circuit

2000-12-08

2004-03-02

Malzahn, David H. (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

06701339

ABSTRACT:

FIELD
The present invention relates generally to pipelined circuits, and more specifically to fast pipelined adder and compressor circuits.
BACKGROUND
Multiplication is one of the major operations in general purpose microprocessors and digital signal processors. The speed with which a multiplier circuit can operate often determines how fast a processor can be clocked.
A fast array multiplier is typically divided into two parts: a partial product summation tree, and a final adder. See G. Goto, T. Sato, M. Nakajima, & T. Sukemura, “A 54×54 Regularly Structured Tree Multiplier,” IEEE Journal of Solid State Circuits, p. 1229, Vol. 27, No. 9, September, 1992.
The partial product summation tree takes up a significant portion of the total multiplication delay and is typically implemented using full adders arranged as three-to-two (3:2) compressors and four-to-two (4:2) compressors. For a discussion of compressors, see Neil H. E. Weste & Kamran Eshragihan, “Principles of CMOS VLSI Design: A Systems Perspective,” 2
nd
Ed., pp. 554-558 (Addison Wesley Publishing YEAR). Increasing the speed of compressors can increase the speed of partial product summation trees, multipliers, and entire integrated circuits.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for fast compressor circuits.


REFERENCES:
patent: 5117133 (1992-05-01), Luebs
patent: 5612632 (1997-03-01), Mahant-Shetti et al.
patent: 5764089 (1998-06-01), Partovi et al.
patent: 5867049 (1999-02-01), Mohd
patent: 5898330 (1999-04-01), Klass
patent: 5900759 (1999-05-01), Tam
patent: 5978827 (1999-11-01), Ichikawa
patent: 6060910 (2000-05-01), Inui
patent: 6121807 (2000-09-01), Klass et al.
patent: 6181180 (2001-01-01), Chen et al.
patent: 6242952 (2001-06-01), Bosshart et al.
patent: 6304123 (2001-10-01), Bosshart
patent: 6397240 (2002-05-01), Fernando et al.
patent: 6437602 (2002-08-01), Friend et al.
patent: 6578063 (2003-06-01), Kojima et al.
patent: 6584485 (2003-06-01), Aoki et al.
patent: 01-206717 (1989-08-01), None
“Power Saving Latch”,IBM Technical Disclosure Bulletin, 39(4), (Apr. 1996), pp. 65-66.
Beaumont-Smith, A., “Reduced Latency IEEE Floating-Point Standard Adder Architectures”,Proceedings of the 14th IEEE Symposium on Computer Arithmetic, (1998), 8 pgs.
Elguibaly, F., “A Fast Parallel Multiplier-Accumulator Using the Modified Booth Algorithm”,IEEE Transactions on Circuits and Systems—II : Analog and Digital Signal Processing, 47(9) (Sep. 2000), pp. 902-908.
Even, G, “On the Design of IEEE Compliant Floating Point Units”,IEEE Transactions on Computers, 49(5), (May 2000), pp. 398-413.
Hokenek, E., “Second-Generation RISC Floating Point with Multiply—Add Fused”,IEEE Journal of Solid-State Circuits, 25(5), (1990), pp. 1207-1213.
Ide, N, “2.44-GFLOPS 300-MHz Floating-Point Vector-Processing Unit for High-Performance 3-D Graphics Computing”,IEEE Journal of Solid-State Circuits, 35(7), (Jul. 2000), pp. 1025-1033.
Lee, K.T., “1 GHz Leading Zero Anticipator Using Independent Sign-Bit Determination Logic”,Symposium on VLSI Circuits Digest of Technical Papers, (2000), pp. 194-195.
Luo, Z., “Accelerating Pipelined Integar and Floating-Point Accumulations in Configurable Hardware with Delayed Addition Techniques”,IEEE Transactions on Computers, 49(3), (Mar. 2000), pp. 208-218.
Panneerselvam, G., “Multiply-Add Fused RISC Architectures for DSP Applications”,IEEE Pac Rim, (1993), pp. 108-111.
Goto, G., et al., “A 54 × 54-b Regularly Structured Tree Multiplier”,IEEE Journal of Solid-State Circuits, vol. 27, 1229-1236, (Sep. 1992).
Klass, F., “Semi-Dynamic and Dynamic Flip-Flops with Embedded Logic”,Proceedings of the Symposium on VLSI Circuits, Digest of Technical Papers, Honolulu, HI, IEEE Circuits Soc. Japan Soc. Appl. Phys. Inst. Electron., Inf. & Commun. Eng. Japan, pp. 108-109, (1998).
Partovi, H., et al., “Flow-Through Latch and Edge-Triggered Flip-Flop Hybrid Elements”,Proceedings of the IEEE International Solid-State Circuits Conference, Digest of Technical Papers and Slide Supplement, NexGen Inc., Milpitas, CA, 40 pgs., (1996).

Affiliated with

Also associated with

Rating

Pipelined compressor circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Pipelined compressor circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pipelined compressor circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3211891