Pipelined bit-serial Galois Field multiplier

Details Pipelined bit-serial Galois Field multiplier Pipelined bit-serial Galois Field multiplier

1986-04-18

1989-01-10

Harkcom, Gary V.

Boots, shoes, and leggings

364746, G06F 738, G06F 752

Patent

active

047978481

ABSTRACT:
A bit-serial pipeline Galois Field multiplier for multiplying an element K(X)=K.sub.m-1 X.sup.m-1 +K.sub.m-2 X.sup.m-2 X.sup.m-2 +. . . +K.sub.0 with another element Y(X)=Y.sub.m-1 X.sup.m-1 +Y.sub.m-2 X.sup.m-2 +. . . +Y.sub.0 to obtain Z.sub.0 =Z.sub.m-1 X.sup.m-1 +Z.sub.m-2 X.sup.m-2 +. . . +Z.sub.0, which is also an element of the field generally defined by P(X)=a.sub.m X.sup.m +a.sub.m-1 X.sup.m-1 +a.sub.m-2 X.sup.m-2 +. . . a.sub.1 X+a.sub.0. The multiplier has an input shift register buffer circuit, an intermediate shift register circuit, an output shift register circuit and multiplying and summing device. The input shift register buffer circuit is configured for serially receiving the K(X) coefficients. The multiplying and summing device receives arrangements of K(X) coefficients and the Y(X) coefficients and operates thereon, by multiplying corresponding pairs of register stage elements and Y(X) coefficients and summing the products. The output shift register circuit receives the resulting coefficients and, beginning m clock intervals after the inputting of K(X) and Y(X) coefficients is started, starts continuous outputing of the product coefficients Z.sub.m-1, Z.sub.m-2, . . . , Z.sub.0.

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