Pipelined analog-to-digital converter with unequal work timing

Details Pipelined analog-to-digital converter with unequal work timing Pipelined analog-to-digital converter with unequal work timing

2005-08-23

2005-08-23

Mai, Lam T. (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000, C341S156000

Reexamination Certificate

active

06933875

ABSTRACT:
A pipelined analog-to-digital converter with unequal work timing comprising several transfer circuits and a decoder is provided. Each transfer circuit includes an analog-to-digital sub-converter, a multiply digital-to-analog converter, a subtractor and an amplifier. The operation time of the analog-to-digital sub-converter is in a sampling time and the operation time of the multiply digital-to-analog converter, the subtractor and the amplifier is in an amplifying time. The amplifying time is longer than the sampling time. The decoder receives the digital bit signals produced by the analog-to-digital sub-converter of the transfer circuit to produce digital signals.

REFERENCES:
patent: 4204198 (1980-05-01), Filipov et al.
patent: 5274377 (1993-12-01), Matsuura et al.
patent: 5541602 (1996-07-01), Opris et al.
patent: 6340944 (2002-01-01), Chang et al.
patent: 6359579 (2002-03-01), Chiang

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