Pipelined analog to digital converter with summing and comparato

Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion

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Details

341155, 341162, H03M 138

Patent

active

049948083

ABSTRACT:
A method and an apparatus are disclosed for analog-to-digital conversion where a reference signal is subtracted from the analog input signal, if needed. The mathematical functions are processed simultaneously with each bit's reference compare decision. The comparator's output control a switch which allows the analog input signal to bypass the summing circuit for certain digital outputs of the comparator. This reduces voltage error and conversion time by keeping the summing circuits out of the signal path if the corresponding bit is not actively represented in the binary word. This allows the converter to avoid synchronization requirements that many other types of A/D converters have.

REFERENCES:
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patent: 3577139 (1971-05-01), Foerster
patent: 4072938 (1978-02-01), Buchanan
patent: 4275386 (1981-06-01), Michel et al.
patent: 4334745 (1982-06-01), Maida
patent: 4611196 (1986-09-01), Fernandez
patent: 4684924 (1987-08-01), Wood
patent: 4760376 (1988-07-01), Kobayashi et al.
patent: 4769628 (1988-09-01), Hellerman

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