Pipelined analog to digital converter with capacitor...

Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion

Reexamination Certificate

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C341S118000

Reexamination Certificate

active

11289045

ABSTRACT:
In a pipelined analog to digital converter with multiple stages of sub-converters, capacitor mismatch error can be reduced by splitting the capacitors into multiple numbers and randomly selecting part of the split capacitors as feedback capacitors. The selection of feedback capacitors can be made according to a digital output, clock phase, stage number of the sub-converter or the combination thereof. The approach of the present invention can be applied to the most significant bit (MSB) stage for a pipelined ADC. Moreover, a method for implementing the same is also proposed.

REFERENCES:
patent: 4760376 (1988-07-01), Kobayashi et al.
patent: 5416485 (1995-05-01), Lee
patent: 6320530 (2001-11-01), Horie
patent: 6420991 (2002-07-01), Yu
patent: 7030801 (2006-04-01), Luo

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