Pipelined analog-to-digital converter with calibration of...

Details Pipelined analog-to-digital converter with calibration of... Pipelined analog-to-digital converter with calibration of...

2008-06-10

2009-11-03

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S120000, C341S161000

Reexamination Certificate

active

07612703

ABSTRACT:
The present invention relates to an analog-to-digital converter, especially to a pipelined analog-to-digital converter with calibration of capacitor mismatch and finite gain error. Comparing with the conventional pipelined analog-to-digital converter, the new analog-to-digital converter comprises more circuit blocks including an extra sub-converter stage, a control clock generator and an error detector, resulting in that each sub-converter stage has two operation modes: normal conversion mode and calibration mode. All of the sub-converter stages share one error detector which amplifies the output of the sub-converter stage in calibration mode. Furthermore, to store the output of the error detector, a memory is used in each sub-converter stage for controlling the gain of amplifier in order to make the error generated by the finite gain of amplifier and the error generated by the capacitance mismatch have the same size but opposite sign. As a result, the two errors can compensate each other to achieve an error-free conversion stage.

REFERENCES:
patent: 6184809 (2001-02-01), Yu
patent: 6232898 (2001-05-01), Nagaraj
patent: 6563445 (2003-05-01), Sabouri
patent: 6784814 (2004-08-01), Nair et al.
patent: 6963300 (2005-11-01), Lee
patent: 7233276 (2007-06-01), Huang
patent: 7355476 (2008-04-01), Kasha et al.

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