Pipelined analog-to-digital converter using zero-crossing...

Details Pipelined analog-to-digital converter using zero-crossing... Pipelined analog-to-digital converter using zero-crossing...

2000-08-24

2002-10-22

Williams, Howard L. (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S162000, C341S161000

Reexamination Certificate

active

06469652

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention is generally directed to analog-to-digital converters (ADCs) and, more specifically, to a zero-crossing capacitor swapping apparatus that improves the differential non-linearity (DNL) and integral non-linearity (INL) characteristics of an ADC.
BACKGROUND OF THE INVENTION
Many low-power, high speed application make use of a pipelined analog-to-digital (A/D) converter (or ADC). Pipelined ADCs provide high data throughput rates, occupy a comparatively small area of an integrated circuit, consume relatively little power, and minimize circuit complexity. Many of these advantages stem from the pipelined arrangement of multiple small A/D conversion stages.
All of the stages work concurrently. The first stage converts the most recent analog sample to a small number of digital bits (e.g., 2 bits) and passes an analog residue signal on to a subsequent stage. Each of the subsequent stages converts the analog residue signal from a preceding stage to digital bits and passes its own analog residue signal to the next stage.
U.S. Pat. No. 5,710,563 to Vu et al. discloses a pipelined ADC comprised of a series of 1.5 bit stages, wherein each stage implements a capacitor swapping circuit. The capacitor swapping circuit uses a sampling capacitor (Cs) and an integrating capacitor (Ci) to alternately sample and amplify input signals in order to reduce capacitor mismatches. The teachings of U.S. Pat. No. 5,710,563 are hereby incorporated by reference into the present disclosure as if fully set forth herein.
Although the capacitor swapping circuit disclosed in U.S. Pat. No. 5,710,563 is effective at reducing differential non-linearity in an ADC, this reduction occurs in the region above the upper boundary and below the lower boundary set by the trip points of the ADC. The capacitor swapping circuit in U.S. Pat. No. 5,710,563 does not compensate for the compression or expansion of code widths between the trip points. Thus, significant amounts of differential non-linearity (DNL) and integral non-linearity (INL) may occurs in the region between the trip points of each ADC stage.
There is therefore a need in the art for improved analog-to-digital converters that exhibit less differential non-linearity (DNL) and less integral non-linearity (INL), particularly in the region between the trip points of each ADC stage. In particular, there is a need for analog-to-digital converters that implement capacitor swapping circuits that improve the DNL and INL characteristics of each stage, including in the region between the trip points.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide, for use in an analog to digital (ADC) converter, an ADC stage capable of receiving a differential analog input signal, quantizing the differential analog input signal to a plurality of digital bits, and generating an output residue signal corresponding to a quantization error of the differential analog input signal. In an advantageous embodiment of the present invention, the ADC stage comprises: 1) a differential amplifier having an inverting input and a non-inverting input and a differential output comprising an inverting output and a non-inverting output; 2) a first capacitor having a first side and a second side and a second capacitor having a first side and a second side, wherein the second side of the first capacitor is coupled to the second side of the second capacitor and to the inverting input of the differential amplifier; 3) a third capacitor having a first side and a second side and a fourth capacitor having a first side and a second side, wherein the second side of the third capacitor is coupled to the second side of the fourth capacitor and to the non-inverting input of the differential amplifier; 4) a switch matrix capable of coupling the first sides of the first, second, third and fourth capacitors to selected ones of the first sides of the first, second, third and fourth capacitors, to selected ones of the inverting and non-inverting outputs of the differential amplifiers, and to selected ones of a positive reference voltage and a negative reference voltage; and 5) a switch control logic circuit capable of detecting a zero reference level crossing, wherein a voltage level on a preceding non-inverting output of a preceding ADC stage transitions from below a voltage level on a preceding inverting output of said preceding ADC stage to a voltage level above said voltage level on said preceding inverting output.
According to one embodiment of the present invention, the switch control logic circuit is capable of controlling the switch matrix.
According to another embodiment of the present invention, prior to detection of the zero-reference level crossing, the switch matrix is set such that the first side of the first capacitor is coupled to the non-inverting output, the first side of the fourth capacitor is coupled to the inverting output, and the first side of the second capacitor is coupled to the first side of the third capacitor.
According to still another embodiment of the present invention, the switch control logic circuit, in response to detection of the zero-reference level crossing, modifies the switch matrix such that the first side of the first capacitor is coupled to the first side of the fourth capacitor, the first side of the second capacitor is coupled to the non-inverting output, and the first side of the third capacitor is coupled to the inverting output.
According to yet another embodiment of the present invention, the switch control logic circuit is capable of detecting a negative trip point crossing, wherein a voltage level on the preceding non-inverting output of the differential amplifier transitions from below a negative trip point to above the negative trip point, wherein the negative trip point is below the zero reference level.
According to a further embodiment of the present invention, the switch control logic circuit is capable of modifying the switch matrix in response to detection of the negative trip point crossing.
According to a still further embodiment of the present invention, the switch control logic circuit is capable of detecting a positive trip point crossing, wherein a voltage level on the preceding non-inverting output of the differential amplifier transitions from below a positive trip point to above the positive trip point, wherein the positive trip point is above the zero reference level.
According to a still further embodiment of the present invention, the switch control logic circuit is capable of modifying the switch matrix in response to detection of the positive trip point crossing.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proxim

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