Pipelined analog to digital converter using digital mismatch...

Details Pipelined analog to digital converter using digital mismatch... Pipelined analog to digital converter using digital mismatch...

2000-11-17

2002-09-24

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S172000

Reexamination Certificate

active

06456223

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates to pipelined analog-to-digital converters, and more particularly relates to methods and apparatus for reducing distortion and noise in such converters.
BACKGROUND OF THE INVENTION
In pipelined analog-to-digital converters (ADCs) a major objective is to achieve maximum spurious-free dynamic range (SFDR). One way in which this is achieved is by reducing spurious signals, such as harmonics. Such spurious signals can arise from the existence of mismatch between the capacitors used in the digital-to-analog converter (DASC) substages of such pipelined ADCs. One way of reducing such spurious signals is to convert such signals into noise, at the expense of signal to noise ratio (SNR). An example of such a technique can be found in co-pending U.S. patent application Ser. No. 09/712,719, filed on Nov. 14, 2000. Such techniques can provide a significant improvement in SFDR. However, it is desired to maintain the improved SFDR due to shuffling while improving SNR of pipelined ADCs that use shuffling.
SUMMARY OF THE INVENTION
The present invention provides, in a pipelined analog-to-digital converter (ADC) having an analog input signal and a digital output signal, and having a plurality of pipelined stages, each such stage having an analog input, an analog output comprising a residue voltage, and a digital output, the stage including a digital-to-analog converter substage having a plurality of capacitors and which are used in a sample-and-hold function and shuffled according to a predetermined procedure, a method for reducing noise generated from the shuffling when the capacitors are mismatched. The method includes the following steps. First, an estimation model is provided of the noise generated from the shuffling. The estimation model includes factors corresponding to mismatches of the capacitors. Mismatches among capacitors in the stage are estimated, based on the monitoring of an output parameter of the stage. A cancellation factor is generated by applying the mismatch estimations to the estimation model. Finally, the cancellation factor is subtracted from an ADC output to substantially reduce and/or effectively cancel the mismatch noise.
These and other features of the invention will be apparent to those skilled in the art from the following detailed description of the invention, taken together with the accompanying drawings.


REFERENCES:
patent: 5144308 (1992-09-01), Norsworthy
patent: 5608722 (1997-03-01), Miller
patent: 6172629 (2001-01-01), Fetterman
patent: 6175321 (2001-01-01), Frannhagen
patent: 6232903 (2001-05-01), Koifman et al.

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