Coded data generation or conversion – Converter calibration or testing
Utility Patent
1998-05-08
2001-01-02
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Converter calibration or testing
C341S155000
Utility Patent
active
06169502
ABSTRACT:
COPYRIGHT AUTHORIZATION
A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent disclosure as it appears in the U.S. Patent and Trademark Office files or records, but otherwise reserves all copyrights whatsoever.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The field of this invention relates to systems, methods, and computer program products relating to analog-to-digital converters (ADCs) and more particularly to calibration systems, methods, and computer program products relating to pipelined ADCs.
2. Description of Related Art
The technical problems of calibrating pipelined analog-to-digital converters (ADCs) have been inadequately addressed in the related art. In particular, the related art addresses the use of a capacitor array for calibration of pipelined ADCs with calibration alterations changing the gain (R) of particular ADC stages to satisfy a predetermined weighting relationship. This is accomplished with successive capacitors that are increasingly lower or higher in capacitance level depending upon the weighting scheme which has been selected. For highly accurate ADC systems, the ratio of largest to smallest capacitor unfortunately results in a requirement to use capacitors of prohibitive capacitance levels. Simply stated, a highly accurate ADC system according to the related art requires very small and very large capacitors. Such a range of capacitance values is difficult and costly to implement with semiconductor materials.
SUMMARY OF THE INVENTION
According to one embodiment of the present invention, a pipelined analog-to-digital converter (ADC) is calibrated to enable production of an n-bit digital output representing an n-2 bit binary word, where “n” is a selected large positive integer, for example without limitation on the order of ten (10). In a multistage analog-to-digital converter (ADC) according to the present invention, each stage includes capacitor circuitry including first and second predetermined capacitors (C
1
and C
2
) and a variable capacitance calibration capacitor (C
cal
) connected to an amplifier at a common node. A multistage ADC stage according to the present invention further includes a comparator, a track and hold circuit, and a source follower circuit. According to one embodiment of the present invention, a multistage ADC system includes at least four stages, each in turn including a capacitor system including first and second predetermined capacitors and a calibration capacitor, an amplifier, a comparator, a tracker, and a source follower. The capacitor system according to the present invention is connected at a common node to the amplifier; the comparator is connected to the first predetermined capacitor; the tracker and source follower are connected to the output of the amplifier; and the source follower is connected to the comparator. According to a method of the present invention, a first predetermined capacitor and a comparator are coupled to an input connection for each of at least four stages. Further, a second predetermined capacitor is coupled to ground in the case of each stage. Then, the first predetermined capacitor is disconnected from the input connection, for each stage, and the second predetermined capacitor is connected to the output of the amplifier in each stage. Further, the output of the amplifier is tracked and the output is provided to the comparator of the subsequent stage to enable a determination of whether this voltage is greater than or less than the reference voltage.
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Johnson Sandra Marie
Welland David R.
Cirrus Logic Inc.
Harris Jonathan
Jeanglaude Jean B.
Sabath Robert P.
Tutkowski Peter T.
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