Pipelined analog-to-digital converter

Details Pipelined analog-to-digital converter Pipelined analog-to-digital converter

2005-12-20

2005-12-20

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S162000

Reexamination Certificate

active

06977606

ABSTRACT:
An arithmetic circuit includes a sample hold portion, an adding portion, a subtracting portion, an A/D sub-converter and a D/A sub-converter. The adding portion adds first and second residual voltages provided from a preceding stage. In a first hold mode, the subtracting portion subtracts an analog voltage from a voltage produced by the addition by the adding portion, and provides a voltage produced by the subtraction as a first residual voltage in this stage to a next stage. In a second hold mode, the subtracting portion interchanges internal capacitors with each other, subtracts the analog voltage from a voltage produced by the addition by the adding portion, and provides a voltage produced by the subtraction as a second residual voltage to the next stage.

REFERENCES:
patent: 5500644 (1996-03-01), Denjean et al.
patent: 6166675 (2000-12-01), Bright
Hisn-Shu Chen et al., A 14-b 10-MSample/s CMOS Pipelined ADC, IEEE Journal of Solid-State Circuits, vol. 36, No. 6, (Jun. 2001), pp. 997-1001.

Affiliated with

Also associated with

Rating

Pipelined analog-to-digital converter does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Pipelined analog-to-digital converter, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pipelined analog-to-digital converter will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3509924