Pipelined analog-to-digital architecture with parallel-autozero

Details Pipelined analog-to-digital architecture with parallel-autozero Pipelined analog-to-digital architecture with parallel-autozero

1988-11-25

1990-01-16

Shoop, Jr., William M.

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

341122, 341155, H03M 144

Patent

active

048946575

ABSTRACT:
A pipelined analog-to-digital converter architecture comprises three pipeline stages wherein the first stage includes a low-resolution flash A/D subconverter (10), two sample-and-hold amplifiers (12 and 14), two D/A converters (16 and 18), and two unity-gain buffers (20 and 22). Parallel-autozero analog processing is accomplished by alternately passing the analog signal through one or the other of two parallel processing channels. The sampled analog signal is delivered to the flash A/D subconverter and the D/A converters simultaneously. The residue from the D/A converters is delivered to the second stage, passing through a flash A/D subconverter (24), an additional D/A converter (26), and alternately through two comparators (28 and 30) each having a gain of eight. The second stage produces and delivers its residual voltage to the final pipeline stage comprising a flash A/D subconverter (32). The unity-gain buffers require a minimal gain-bandwidth product for a given sampling rate and allow the architecture to operate at high speed, while the first stage D/A converters provide good accuracy.

REFERENCES:
patent: 4611196 (1986-09-01), Fernandez
patent: 4695825 (1987-09-01), Bloy et al.
patent: 4745394 (1988-05-01), Cornett
patent: 4774499 (1988-09-01), Mapleston
Dingwall et al., "An 8-MHz CMOS Subranging 8-Bit A/D Converter", IEEE J. of Solid-State Circuits, Dec. 1985, pp. 1138-1143.
Lewis et al., "A Pipelined 5-Msample/s 9-Bit Analog-to-Digital Converter", IEEE J. of Solid-State Circuits, Dec. 1987, pp. 954-961.
Takemoto et al., "A Fully Parallel 10-Bit A/D Converter with Video Speed", IEEE J. of Solid-State Circuits, Dec. 1982, pp. 1133-1138.

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