Pipelined address memories, and systems and methods using the sa

Details Pipelined address memories, and systems and methods using the sa Pipelined address memories, and systems and methods using the sa

1996-06-14

1998-04-28

Le, Vu A.

Static information storage and retrieval

Addressing

Plural blocks or banks

365203, 365221, G11C 700

Patent

active

057454280

ABSTRACT:
A dynamic random access memory device 200 includes circuitry 202 for generating a plurality of internal row address strobes. A plurality of memory banks 201 are included, each having an array 203 of dynamic random access cells and associated dynamic control circuitry. A first one of the memory banks 201 enters precharge in response to a precharged cycle of a first one of the internal row address strobes. Simultaneously, a second one of the banks 201 enters an active cycle in response to an active cycle of a second one of the internal address strobes.

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