Pipelined accumulators

Details Pipelined accumulators Pipelined accumulators

2003-10-01

2008-09-09

Mai, Tan V (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

07424503

ABSTRACT:
Pipelined digital accumulators. Parallel digital accumulators for use in digital signal processing are improved through pipelining. An accumulator is partitioned into a plurality of pipelined stages, and the pipeline delay is used to reduce the effect of carry propagation through the accumulator. While input and output delay registers are used in the accumulator partitions, the output delay registers are not needed if the results of those partitions are not needed in subsequent stages of computation. If phase coherence is not needed, input delay registers may not be needed on accumulator partitions. In the limiting case of one bit per partition, the effective speed of the pipelined accumulator is equivalent to the speed of a single bit accumulator stage.

REFERENCES:
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patent: 6138136 (2000-10-01), Bauer et al.
Fang Lu, Henry Samueli, Jiren Yuan and Christer Svensson—“A 700-MHz 24-b Pipelined Accumulator In 1.2 um CMOS For Application As A Numerically Controlled Oscillator”: IEEE Journal Of Solid-State Circuits, vol. 28, No. 8, Aug. 1993; pp. 878-886.
Edward Merlo, Kwang-Hyun Baek, Myung-Jun Choe—“Exponential Split Accumulator For High-Speed Reduced Area Low-Power Direct Digital Frequency Synthesizers”; Rockwell Scientific Company, 1049 Camino dos Rios, Thousand Oaks, CA 91360; pp. 249-252.
Matthew Thompson—“Low-Latency, High-Speed Numerically Controlled Oscillator Using Progression-Of-States Technique”; IEEE Journal Of Solid-State Circuits, vol. 27, No. 1, Jan. 1992; pp. 113-117.

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