Pipelined A/D converter

Details Pipelined A/D converter Pipelined A/D converter

1992-07-02

1993-12-28

Hoff, Marc S.

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

341156, H03M 142

Patent

active

052743772

ABSTRACT:
There is disclosed a pipelined A/D converter including a plurality of A/D-D/A sub-blocks and one A/D sub-block successively connected in cascade form to determine a conversion output by several partial bits beginning from the most significant bit. Each of A/D-D/A sub-blocks includes a sample-and-hold circuit for successively sampling and holding an input analog signal fed to the sub-block, a partial A/D converter for performing A/D conversion on a hold output of this sample-and-hold circuit, a latch circuit for latching outputs of the partial A/D converter, a D/A converter for inversely converting outputs of the latch circuit to an analog signal, and a chopper amplifier for sampling the hold output of the sample-and-hold circuit with a delay of half a period, amplifying a difference between the sampled value and the inverse conversion output of the D/A converter during a succeeding interval of amplify mode, and outputting the amplified difference to a sub-block of a succeeding stage as a conversion residue.

REFERENCES:
patent: 4875048 (1989-10-01), Shimizu et al.
patent: 4908621 (1990-03-01), Polonio et al.
patent: 5043732 (1991-08-01), Robertson et al.
patent: 5047772 (1991-09-01), Ribner
patent: 5159342 (1992-10-01), Yotsuyanagi
IEEE International Solid-State Circuits Conference, pp. 210-211, 1987.
IEEE 1992 Symposium on VLSI Circuits, Seattle, WA, Jun. 3-5, 1992, pp. 98-99.

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