Pipeline-type serial multiplier circuit

Details Pipeline-type serial multiplier circuit Pipeline-type serial multiplier circuit

1988-09-16

1991-02-19

Shaw, Dale M.

Boots, shoes, and leggings

G06F 752

Patent

active

049949977

ABSTRACT:
A pipeline-type serial multiplier having a cellular structure, each cell comprising an adder which operates on 3 one-bit data x, y, c and which determines the result v modulo 2 and the carry c.sub.o of the addition of x, y, and c. Each adder simultaneously determines a data c.sub.1 which is the modulo 2 result of the addition of x, y, c.sub.o. This enables the exact final result of a multiplication of a data A of n bits by a data B of p bits to be obtained in two successive segments: a segment L which is formed by the p bits of lowest digital weight and a segment H which is formed by the n bits of the highest weight. The output rate is F
, where F is the clock frequency. The multiplier circuits can be cascaded under the control of an external signal. They can also be connected in parallel in order to add the results of two multiplications.

REFERENCES:
patent: 4799182 (1989-01-01), Marwood
N. F. Benschop et al., Compact NMOS Array Multipliers with Inverting Full Adders, Philips J. Res., vol. 36, pp. 173-194, (1981).

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