Boots – shoes – and leggings
Patent
1995-04-17
1996-01-16
Lall, Parshotam S.
Boots, shoes, and leggings
395800, 364DIG1, 3642318, G06F 104
Patent
active
054856035
ABSTRACT:
An image processing pipeline system and method utilizes a cascade of data processing modules for processing a stream of pixel data units organized in successive groups, which are presented to the system input, the groups being separated from one another by time slots consisting of dead time intervals produced, for example, by line or frame fly-back. The modules are controlled by control signals produced by sampling circuit type characteristic circuits in response to control pulses from a control signal source. The control signals applied to the modules are in synchronism with the presence of data units at the system input, and are absent during the dead time intervals. In order to avoid loss of information due to processing delays if data transport between the modules takes place during an occurrence of a dead time interval, a monitoring circuit stops or pauses processing by the modules during that time interval of data units to reach the system input prior to the interval.
REFERENCES:
patent: 4916659 (1990-04-01), Persoon et al.
patent: 4965717 (1990-10-01), Cutts, Jr. et al.
patent: 5046190 (1991-09-01), Daniel et al.
"The Architechture of Pipelined Computers" P. M. Kogge, Hemisphere Publishing 1981, pp. 30-31.
Nijholt Geert
Persoon Eric H. J.
Ellis Richard L.
Lall Parshotam S.
Slobod Jack D.
U.S. Philips Corporation
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