Pipeline system for executing predicted branch target instructio

Details Pipeline system for executing predicted branch target instructio Pipeline system for executing predicted branch target instructio

1990-12-10

1993-11-23

Harrell, Robert B.

Boots, shoes, and leggings

3642292, 3642318, 3642613, 3642617, 364DIG1, G06F 938

Patent

active

052652130

ABSTRACT:
A pipeline instruction processor for executing instructions stored in an instruction memory, including a plurality of branch instructions. The instruction processor includes a branch target buffer which contains target instructions and target addresses corresponding to branch instructions. The target instruction data is indexed according to the address of the instruction which precedes the branch instruction. Also included in the branch target buffer is history data indicating whether the branch was taken. The instruction processor also includes two execution units. The present invention employs logic which allows a branch instruction and its target instruction stored in the branch target buffer to be executed concurrently in the two execution units according to the history data stored in the branch target buffer. Since the branch instructions and their target instructions are executed during the same cycle, branch instructions appear to be executed in zero cycles.

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