Pipeline stop circuit for external memory access

Details Pipeline stop circuit for external memory access Pipeline stop circuit for external memory access

1997-12-30

2000-04-11

Ngo, Chuong Dinh

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

712205, 712245, G06F 738, G06F 900, G06F 922

Patent

active

060498161

ABSTRACT:
A pipeline stop circuit for an external memory access which is capable of effectively performing a pipeline operation by temporarily stopping a pipeline operation, which is being operated, until data are prepared in the memory accessed, when accessing an external memory or a slow internal memory. The processor includes a program selection unit for carrying one of a program from an internal RAM and a program from an external program memory onto a program bus in accordance with an external program request signal and an external memory preparation signal, an instruction fetch unit for fetching the program carried on the program bus in accordance with a program wait signal and a data wait signal and outputting an instruction, an instruction decoding unit for decoding an instruction from the instruction fetch unit, and a control signal generation unit for fetching a decoding signal from the instruction decoding unit, outputting a control signal, and stopping a fetching operation of the decoding signal when the program wait signal or data wait signal is activated.

REFERENCES:
patent: 5050068 (1991-09-01), Dollas et al.
patent: 5222241 (1993-06-01), Murakami et al.
patent: 5237667 (1993-08-01), Murakami et al.
patent: 5442799 (1995-08-01), Murakami et al.
patent: 5594914 (1997-01-01), Coomes et al.
patent: 5710914 (1998-01-01), Verbauwhede et al.

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