Pipeline scheduler with fairness and minimum bandwidth...

Details Pipeline scheduler with fairness and minimum bandwidth... Pipeline scheduler with fairness and minimum bandwidth...

2006-05-09

2006-05-09

Phunkulh, Bob A. (Department: 2661)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S230000, C370S474000

Reexamination Certificate

active

07042883

ABSTRACT:
A pipeline scheduler provides a minimum bandwidth guarantee by transporting cells from an input port to an output port in a two-phased approach. Cells that conform to a minimum cell rate (MCR) are selected from queues at the input port and arranged into supercells for transport to the output port, followed by nonconforming cells, to guarantee fairness by using scheduling modules to build the supercells first for conforming cells, and then for nonconforming cells. Reservation vectors are used to permit the same time slot of the next frame to be reserved by a first queue, and the same time slot of the following time frame to be held for reservation by a second queue, to ensure equal time slot access by the first and second queues over successive time frames.

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Naoki Matsuoka et al.; “A Study on Terabit Switch Architecture with QoS Control”, Technical Report of IEICE, SSE2000-40, vol. 100, No. 79; May, 2000; 8 pages. (Abstract in English only).

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