Pipeline processsor

Details Pipeline processsor Pipeline processsor

1996-04-08

1998-03-03

Eng, David Y.

G06F 932, G06F 938

Patent

active

057245630

ABSTRACT:
According to the present invention, a pipeline processor is provided for executing a predictive branch instruction defining a number of at least one instruction which is to be executed in succession after the predictive branch instruction is given before a control flow is changed. The pipeline processor includes: a program counter for holding an address of an instruction to be fetched; an instruction memory for outputting an instruction corresponding to the address held by the program counter; an instruction register for fetching and holding the instruction output from the instruction memory; an instruction decoding section for decoding the instruction held by the instruction register, thereby judging whether or not the instruction is the predictive branch instruction; a counter section for holding a counter value and comparing the counter value with a predetermined threshold value, the counter value being initialized to the number defined by the predictive branch instruction and being decremented in synchronization with an increment of the program counter; an adder for incrementing the address held by the program counter and providing the incremented address as a sequential instruction address; a branch target address register for providing a branch target address of the predictive branch instruction; and a selector for selecting one of the sequential instruction address and the branch target address of the predictive branch instruction in accordance with a comparison result obtained by the counter section.

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