Pipeline processor with self timed data transfer

Details Pipeline processor with self timed data transfer Pipeline processor with self timed data transfer

1991-03-28

1994-01-18

Bowler, Alyssa H.

Boots, shoes, and leggings

395250, 364DIG1, 3642318, 36494834, 36496426, 36518905, G06F 1300, G06F 1342, G11C 1900

Patent

active

052805972

ABSTRACT:
An improved self-timed pipeline processor is provided with self-timed data transfer, thereby making it possible to control exclusively the memory reading and memory writing accesses of individual pipeline stages. The self-timed pipeline processor prohibits memory reading during memory writing and vice versa. In addition, the pipeline processor temporarily prevents the transfer of data to a next-accessing pipeline stage when the memory address presently being accessed is the same as the address to be accessed next, thereby preventing malfunction of the processor.

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Digest of Technical Papers, 1989 Symposium on VLSI Circuits, pp. 123-124, Takata et al.

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