Pipeline processor with enhanced method and apparatus for restor

Details Pipeline processor with enhanced method and apparatus for restor Pipeline processor with enhanced method and apparatus for restor

1997-02-07

1998-05-26

Harrell, Robert B.

G06F 942

Patent

active

057581126

ABSTRACT:
Redundant mapping tables for use in processors that rename registers and perform branch prediction is presented. The redundant mapping tables include a plurality of primary RAM cells coupled to a plurality of redundant RAM cells. In the event of a branch instruction, the redundant RAM cells can save the contents of the primary RAM cells in a single clock cycle before the processor decodes and executes subsequent instructions along a predicted branch path. Should the branch instruction be mispredicted, the redundant cells can restore the primary RAM cells in a single clock cycle. A branch stack, coupled to the redundant mapping tables, updates restored mapping tables with changes made for preceding instructions that were decoded in parallel with the branch instruction. A plurality of levels of redundant RAM cells may be used to enable the nesting of a plurality of branch predictions at any one time.

REFERENCES:
patent: 5134561 (1992-07-01), Liptay
Cocke, et al., "The Evolution Of RISC Technology At IBM," IBM J. Res. Develop., vol. 34 No. 1, pp. 4-36(Jan., 1990.).

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