Patent
1997-07-07
1998-09-29
Lim, Krisna
395591, G06F 938, G06F 930
Patent
active
058156968
ABSTRACT:
There is provided an instruction supply unit 20 for generating addresses for each instruction when an interrupt occurs, from an interrupted instruction until an instruction to be executed later by the number of instructions contained in a delay slot of the instruction an interrupt control unit 50 for storing each address thus generated, and an instruction executing unit 30 for successively reading out each of the stored addresses from the address of the interrupted address after the interrupt processing is completed. The instruction executing unit 30 executes a branch instruction to the address which is first read out. Thereafter, with respect to the addresses which are read out secondly and subsequently, if the address is the branch destination address of the branch instruction, the instruction executing unit 30 executes the branch instruction to the address, and if the address is not the branch destination address, it executes an NOP instruction. Accordingly, even when the instruction length is not fixed, the interrupt can be accurately processed.
REFERENCES:
patent: 4881196 (1989-11-01), Kodama et al.
patent: 5099419 (1992-03-01), Nomura
patent: 5287522 (1994-02-01), Brown et al.
patent: 5566338 (1996-10-01), Kodama et al.
patent: 5579525 (1996-11-01), Suzuki
Kojima Keiji
Kurokawa Yoshiki
Nishioka Kiyokazu
Nojiri Tohru
Tanaka Kazuhiko
Hitachi , Ltd.
Lim Krisna
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