Pipeline processor for mixed-size FFTs

Details Pipeline processor for mixed-size FFTs Pipeline processor for mixed-size FFTs

1991-11-08

1994-03-08

Mai, Tan V.

Boots, shoes, and leggings

G06F 15332

Patent

active

052933300

ABSTRACT:
A method is described for performing fast Fourier transforms (FFTs) of various sizes simultaneously in one pipeline processor. The processor consists of several stages of butterfly computational elements alternated with delay-switch-delay (DSD) modules that reorder the data between the butterfly stages. The sequence of the DSD operations in the pipeline is made arbitrary. This flexibility in choosing the DSD sequence enhances the fault tolerance operation of the pipeline in case of a partial failure in one or more of the DSD modules. If one of the DSDs is no longer capable of operating in its prescribed mode, it is assigned a different operating mode. All the required changes are performed by software control without the need to physically remove or interchange any components. By properly ordering the input data to the pipeline and the butterfly twiddle factors, and by bypassing some butterfly elements for the smaller size transforms, it is shown that any mixture of FFT sizes can be performed. FFTs of radix 2, radix 4, and mixed 2 and 4 are considered. In each case, the principles of operation are explained and examples of timing diagrams are given.

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