Electrical computers and digital processing systems: processing – Processing architecture – Distributed processing system
Reexamination Certificate
1997-10-21
2002-10-01
Lee, Thomas (Department: 2154)
Electrical computers and digital processing systems: processing
Processing architecture
Distributed processing system
C712S042000, C712S200000, C712S201000, C712S248000
Reexamination Certificate
active
06460129
ABSTRACT:
BACKGROUND OF THE INVENTION
1) Field of the Invention
The present invention relates to a pipeline operation method in which plural operational units including pipeline operational units (e.g. multipliers) and non-pipeline operational units (e.g. dividers) share a single writing port to perform an operational process. The present invention also relates to a pipeline operation device in which plural operational units including pipeline operational units (e.g. multipliers) and non-pipeline operational units (e.g. dividers) share a single writing port to perform an operational process.
2) Description of the Related Art
Generally, in order to write operation results from plural operation units into a floating-point register (hereinafter referred to as FR), there are (1) a writing method in which a FR includes writing ports corresponding to the number of operation units and the operation result from each operation unit is ready to write to the FR without controlling the writing timing, and (2) a writing method in which plural operation units share one writing port and the operation result of each operation unit is written to the FR while the writing timing is being controlled.
Today's computers perform the pipeline operation shown in
FIG. 6
for a command execution. Referring to
FIG. 6
, numeral
2
represents an instruction queue,
3
represents an instruction register,
4
represents a decoder (DEC),
5
represents a pipelinne control circuit,
6
represents a floating-point register (FR), and
9
represents a pipeline operation unit. The elements will be explained in detail with reference to FIG.
8
.
In the pipeline operation, the following instruction is started before the previous instruction has been completed. A process which can be divided into plural steps is distributed to plural processing mechanisms corresponding to each step land subjected to a process. But datum to be processed does not pass the same processing unit plural times.
The pipeline operation, as shown in
FIG. 6
, is formed of an instruction selection stage Sf, a register reading stage Ff, operation execution stages E
1
f to Emf, and a writing stage Wf. The instruction selection stage Sf is a stage which selects an instruction. The register reading stage Ff is a stage which translates or decodes an instruction and reads data out of a register. The operation execution stages E
1
f to Emf are stages which execute an arithmetic operation (the case where an arithmetic operation is performed in the m-th stage, where m is the number of operation cycles (the number of operation execution stages) of the pipeline operation unit
9
in FIG.
6
). The writing stage Wf is a stage which writes an operation result into a register.
In the pipeline operation, the pipeline control circuit
5
selects an instruction to be processed out of the instruction queue
2
in the first instruction selection stage Sf to write it into the instruction register
3
. The decoder
4
decodes an instruction selected in the instruction selection stage Sf in the register reading stage Ff and then reads data out of the FR
6
according to the decoded result.
Thereafter, an actual operation is executed using data read out of the operation unit
9
in the operation execution stages E
1
f to Emf. Then the final operation result obtained in the operation execution stage Emf is written into the FR
6
in the writing stage Wf.
In the above-mentioned operation, plural stages are carried out in parallel (overlap execution) while they are shifted by one cycle (one stage). Thus in every cycle, data is input and the operation result is output. The pipeline operation unit
9
can operate the above-mentioned operation.
In addition to the pipeline operation unit
9
such as a multiplier that can perform the pipeline operation, there is a non-pipeline operation unit such as a divider which cannot operate the pipeline operation or cannot operate plural stages in parallel (overlap execution).
When the non-pipeline operation unit, as shown in
FIG. 7
, begins an arithmetic operation, it cannot execute the register reading stage Ff until the completion of the arithmetic operation or for (n+1) &tgr;, where n is the number of operation cycles (the number of operation execution stages) of the non-pipeline operation unit and &tgr; is time (control period) taken for one cycle (one stage), so that the next data cannot be received. In
FIG. 7
, numeral
7
represents a non-pipeline operation unit.
Hence, non-pipeline operation unit cannot perform a pipeline operation as the pipeline operation unit
9
.
Generally, the divider being a non-pipeline operation unit takes, much time for an arithmetic operation and has a small appearance frequency as an instruction.
As shown in
FIGS. 8 and 10
, generally, the non-pipeline operation unit
7
such as a divider and the pipeline operation unit
9
which can perform a pipeline operation often share the writing port
6
a
of the FR
6
.
However, where the writing port
6
a
is shared, two operation units
7
and
9
cannot simultaneously execute an writing operation to the FR
6
. Therefore, two methods have been conventionally used as follows:
(a) The pipeline operation unit
9
is inhibited in its operation while the non-pipeline operation unit
7
is operating.
(b) The writing stage Wf of the pipeline operation unit
9
is delayed by 1&tgr; only when the writing stage Wf of the non-pipeline operation unit
7
is overlapped with the writing stage Wf of the pipeline operation unit
9
.
The configuration of the pipeline operation device adopting the former case (a) is shown in FIG.
8
. In
FIG. 8
, numeral
1
represents an operation pipeline control unit. The operation pipeline control unit
1
receives an arithmetic instruction from a control unit (not shown) and then subjects the entire operation unit including the operation units
7
and
9
, and the FR
6
to a pipeline control. The operation pipeline control unit
1
includes an instruction queue
2
, an instruction register
3
, a decoder (DEC)
4
, and a pipeline control circuit
5
.
The instruction queue
2
holds an arithmetic instruction sent from a control unit (not shown). The instruction register
3
is selected by the pipeline control circuit
5
and then stores temporarily an arithmetic instruction read out of the instruction queue
2
.
The decoder
4
decodes an arithmetic instruction stored in the instruction register
3
and then sends the decoded results as a register number to the FR
6
, an instruction signal to operation units
7
and
9
, and an arithmetic start signal to the pipeline operation unit
9
.
The pipeline control circuit
5
issues an instruction selection signal to the instruction queue
2
; issues an interlock signal in the register reading stage Ff to the decoder
4
; and then controls the pipeline of the operation unit during the operation of the non-pipeline operation unit
7
.
The FR
6
reads and stores data corresponding to the address designated by the operation pipeline control unit
1
and stores the operation result of the operation units
7
and
9
.
The non-pipeline operation unit
7
such as a divider starts its arithmetic operation in response to an operation start signal from the operation pipeline control unit
1
(decoder
14
). The pipeline operation unit
9
such as a multiplier can execute the above-mentioned pipeline operation and starts arithmetic operation when an operation start signal is received from the operation pipeline control unit
1
(decoder
4
).
As shown in FIGS.
9
(
a
)-
9
(
c
) after the non-pipeline operation unit
7
starts its operation (FIG.
9
(
a
)), the pipeline operation unit
9
sharing the writing port
6
a
may start its arithmetic operation (FIG.
9
(
b
)). In this case, after the completion of the instruction selection stage Sf, when the pipeline control circuit
5
outputs an interlock signal to the decoder
4
, the pipeline operation unit
9
does not start its arithmetic operation because it is interlocked in the register reading stage Ff.
After the completion of the arithmeti
Fujioka Shuntaro
Moriwaki Shinichi
Ohta Hidenobu
Yanagida Masahiro
Hu Jinsong
Lee Thomas
Staas & Halsey , LLP
LandOfFree
Pipeline operation method and pipeline operation device to... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Pipeline operation method and pipeline operation device to..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pipeline operation method and pipeline operation device to... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2936576