Boots – shoes – and leggings
Patent
1985-06-25
1989-01-31
Shaw, Gareth D.
Boots, shoes, and leggings
G06F 900
Patent
active
048021130
DESCRIPTION:
BRIEF SUMMARY
CROSS REFERENCE TO RELATED APPLICATIONS
This application is related to U.S. applications having Ser. Nos. 755,321; 758,664 and 752,190.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a pipeline control system, particularly to a pipeline control system in a data processing unit of the pipeline control type wherein the processing is carried out at a high speed when a branching instruction is executed.
2. DESCRIPTION OF THE RELATED ART
Data processing units of the pipeline control system type, which execute the processes of instruction fetch and execution of relevant instructions using pipeline control systems of this type are accompanied by problems concerning how to reduce the "waiting" condition time which is generated when needed data or instructions do not exist in the cache memory and concerning how to execute alternate processing smoothly when the instruction sequence is altered due to the establishment of a branching condition or an interruption.
The problem associated with the "waiting" condition can be solved to a certain degree by increasing the capacity of the cache memory, however, the problem related to alternate processing of an instruction sequence concerning how to quickly read the branching address instruction of a branching instruction still remains even with an increased size cache memory.
Meanwhile, when forming certain logical functions the recent trend to high density integration of logical circuits must be considered, especially when the number of logical elements increases, and if the hardware can reduce the number of input/output terminals of each logical block, performance of the system as a whole can be improved.
The prior art is first explained and the problems of the prior are discussed. FIG. 1 is a schematic profile of a pipeline operation in a data processing unit with pipeline control according to the prior art. In this figure, I1-I3 are pipeline stages for instruction fetch, while Pl-P6 are pipeline stages for execution of instructions, namely the operand fetch and calculation. The general operations of a data processing unit with pipeline control are explained with reference to FIG. 1. First, the heading address of a microprogram to be executed is loaded into the instruction address register (hereinafter referred to as IAR) 1A from a service processor (not shown) in stage Il of the pipeline of this data processing unit. In this case, since "0" is loaded into the instruction fetch constant register (hereinafter referred to as IFKR) 1B, the content of IAR 11 is directly loaded into the execution address register (hereinafter referred to as EAR) through the adder (A) 2A in stage I2. The cache memory 4 is accessed by EAR 3 and thereby relevant micro instructions are read out and loaded into the instruction word register (hereinafter referred to as IWR) at the end of stage I3.
After the first instruction is read as explained above, a fixed value of "8" is loaded into IFKR 1B from the instruction fetch control part (IFC) 1, and added to the content of IAR 1A by the adder (A) 2A, and the execution address is calculated and loaded into the EAR 3. As a result, the micro instruction read into IWR 5 is loaded in units of 8 bytes. The IWR 5 is generally composed of a multi-stage shift register and the boundary address of plural instructions stored in the IWR 5 can be obtained from a pointer register (not shown).
A selector (SEL) 6 selects the instruction to be executed in the pipeline in accordance with the address indicated by the pointer register
When the relevant instruction is selected by the selector (SEL) 6 in stage Pl of the pipeline, the operation code area of the instruction is shifted via the operation code registers P20P-P60P(8) corresponding to the stages P2-P6 and is used when the instruction is executed at respective stages.
The register designation area of the instruction is decoded, the general purpose register is accessed based on the decoded address and the base address and index value are respectively read into the base regi
REFERENCES:
patent: 4040031 (1977-08-01), Cassonnet
patent: 4200927 (1980-04-01), Hughes et al.
EP 8490 4162--Supplementary European Search Report.
Oinaga Yuji
Onishi Katsumi
Otsuyama Kohei
Fujutsu Limited
Mills John G.
Shaw Gareth D.
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