Pipeline circuit for timing adjustment of irregular valid and in

Details Pipeline circuit for timing adjustment of irregular valid and in Pipeline circuit for timing adjustment of irregular valid and in

1989-05-12

1992-08-25

Lee, Thomas C.

Boots, shoes, and leggings

364DIG1, 3642318, 364270, 3642663, 395375, G06F 1314

Patent

active

051426854

ABSTRACT:
A pipeline circuit is capable of adjusting the timing of data, in a data processing system for ensuring processing, even if the input timings of different data are irregular or the input data are invalid. This is achieved by generating a selection signal, which is input to a data holding circuit. The selection signal determines the particular register in which a datum is stored. The value of the selection signal is determined by an input indicating signal, which indicates whether a particular datum is valid or invalid. When the data is valid the selection signal is shifted to the next value, indicating the next higher register, and when the data is invalid the selection signal maintains the value it had for the previous datum.

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patent: 4782441 (1988-11-01), Inagami et al.
patent: 4783783 (1988-11-01), Nagai et al.
patent: 4802120 (1989-01-01), McCoy

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