Pipeline-based reconfigurable mixed-radix FFT processor

Details Pipeline-based reconfigurable mixed-radix FFT processor Pipeline-based reconfigurable mixed-radix FFT processor

2007-01-08

2010-12-07

Bullock, Jr., Lewis A (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S400000, C708S409000

Reexamination Certificate

active

07849123

ABSTRACT:
The present invention discloses a fast Fourier transform (FFT) processor based on multiple-path delay commutator architecture. A pipelined architecture is used and is divided into 4 stages with 8 parallel data path. Yet, only three physical computation stages are implemented. The process or uses the block floating point method to maintain the signal-to-noise ratio. Internal storage elements are required in the method to hold and switch intermediate data. With good circuit partition, the storage elements can adjust their capacity for different modes, from 16-point to 4096-point FFTs, by turning on or turning off the storage elements.

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