Pipeline arithmetic and logic system with clock control function

Details Pipeline arithmetic and logic system with clock control function Pipeline arithmetic and logic system with clock control function

1996-10-04

1998-06-23

Lim, Krisna

395376, G06F 938

Patent

active

057713766

ABSTRACT:
A pipeline arithmetic and logic system capable of adjusting operational timings among stages without using an NOP instruction, providing a size reduction of its control section. The system has a decoder set including decoder groups divided into a decoder group for controlling an arithmetic section unit, a register file unit and a program counter unit, and a decoder for control of an address unit, and further including a clock control unit controlled by the address unit control decoder. A clock signal from an external source is directly fed to the address unit while being fed through the clock control unit to the other units. When fetching a data transfer instruction and repeatedly executing an MA stage twice, the system stops the clock control unit at the execution of the first MA stage to inhibit the operations of the units other than the address unit.

REFERENCES:
patent: 3840861 (1974-10-01), Amdahl et al.
patent: 4365311 (1982-12-01), Fukunaga et al.
patent: 4471432 (1984-09-01), Wilhite et al.
patent: 5134562 (1992-07-01), Hattori et al.

Affiliated with

Also associated with

Rating

Pipeline arithmetic and logic system with clock control function does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Pipeline arithmetic and logic system with clock control function, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pipeline arithmetic and logic system with clock control function will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1400732