Pipeline architecture for multi-slot wireless link processing

Details Pipeline architecture for multi-slot wireless link processing Pipeline architecture for multi-slot wireless link processing

2005-11-02

2009-06-02

Torres, Juan A (Department: 2611)

Pulse or digital communications

Receivers

C375S229000, C375S350000, C375S346000, C455S307000, C708S300000

Reexamination Certificate

active

07542523

ABSTRACT:
A wireless communication device processes N Radio Frequency (RF) bursts contained within N slots of a digital communications time divided frame, wherein N is a positive integer greater than one. The wireless communication device includes an RF front end, a baseband processor, and an equalizer module. The RF front end is operable to receive the plurality of received RF bursts and to convert the RF bursts to corresponding baseband signals. The baseband is operable to receive the baseband signals, to pre-equalization process the baseband signals to produce processed baseband signals, and to post-equalization process soft decisions. The equalizer module is operable to equalize the processed baseband signals to produce the soft decisions. These RF bursts may be contained in adjacent slots or, in non-adjacent slots, or in a combination of adjacent slots and non-adjacent slots.

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