Pipeline architecture for generating video signal

Details Pipeline architecture for generating video signal Pipeline architecture for generating video signal

1990-03-22

1992-12-29

Harkcom, Gary V.

G06F 1562

Patent

active

051758091

ABSTRACT:
A symbol generator with pipeline architecture comprised of a series of processing stages that regenerate a complete video data signal for each display field. Any symbol in a display may be moved in real time and independently of any other symbol, because the display is regenerated for each and every field. The symbol generator includes a cpu microprocessor, vertical sorter, boundary generator, horizontal sorter, and color palette.

REFERENCES:
patent: 4364037 (1982-12-01), Walker
patent: 4831557 (1989-05-01), Murata
patent: 4972330 (1990-11-01), Matsushiro et al.
Dyer, Scott et al., "A Vectorized Scan-Line Z-Buffer Rendering Algorithm", IEEE CG & A, Jul., 1987.
Smith, Arthur et al., "A New Dimension in Broadcast Graphics", SMPTE Journal, Sep. 1982.
Weinstock, Neal, "CGI: An Introduction to the Technology", E-ITV, Apr., 1987.
IEEE Transactions on Computers, vol. 1, Jan. 1981, "The Edge Flag Algorithm-A Fill Method for Raster Scan Displays", Bryan D. Ackland.

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