Coded data generation or conversion – Converter calibration or testing
Reexamination Certificate
2001-07-27
2002-12-03
Young, Brian (Department: 2819)
Coded data generation or conversion
Converter calibration or testing
C341S144000, C341S155000, C341S161000
Reexamination Certificate
active
06489904
ABSTRACT:
BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates generally to analog-to-digital converters, hereinafter referred to as ADCs, and, more particularly, to a pipeline ADC employing internal digital calibration to improve linearity of the ADC.
Multi-stage pipeline ADCs exhibit the distinct advantage of achieving a high sample rate for low power, compared to other architectures such as flash and successive approximation. For this reason, pipeline ADCs have been widely used in many applications, especially those that can tolerate this architecture's inherent delay between the time the input signal is sampled and the time the digitized output becomes available. Exemplary of these applications are image capture applications such as ultrasound, video cameras, scanners, etc., as well as intermediate frequency demodulation in wireless communications applications and various laboratory instrumentation applications.
Recent advancements in these applications have pushed the resolution requirement for ADCs to 12 bits or higher. In order to meet this level of performance demand, a number of digital domain error calibration techniques have been developed. In the case of multi-stage pipeline ADCs with 1.5 bits per stage, U.S. Pat. No. 5,465,092 to Mayes et al., U.S. Pat. No. 5,499,027 to Karanicolas et al., and U.S. Pat. No. 5,510,789 to Lee describe a means for detecting and correcting errors in reconstruction digital-to-analog converters in each stage. This 1.5 bits per stage architecture is simple to design and also to calibrate because all stages have the same circuit topology. Its disadvantage is that it inherently consumes more power than a multi bits per stage counterpart described in Cline et al., “A Power Optimized 13-b 5M samples/s Pipelined Analog-to-Digital Converter in 1.2 um CMOS,” IEEE Journal of Solid State Circuits, March, 1996, pp. 294-303.
Lee et al., “Digital-Domain Calibration of Multistep Analog-to-Digital Converters,” IEEE Journal of Solid State Circuits, December, 1992, pp. 1679-1688, proposes a means of digitally calibrating a multi bits per stage pipeline ADC. This reference teaches a means for detecting an error between two adjacent codes of a multiplying DAC (MDAC) composed of a capacitor array and an operational transconductance amplifier (OTA), by the subsequent stages of the ADC. As each code transition error or differential linearity error (DLE) is measured, it is digitally accumulated to derive the linearity error of all codes or integral linearity error (ILE). As acknowledged by the authors in this reference, this digital accumulation technique inherently suffers from digital truncation errors, which increase as the resolution of each stage increases.
The prior art circuits of
FIGS. 1A and 1B
serve to measure an MDAC's segment error for code transition from j to j+1. The MDAC is composed of the operational transconductance amplifier (OTA), feed back capacitor Cf, the binary weighted capacitor array, the sampling switch SW, and other switches that selectively connect bottom plates of the capacitor array to terminals Vref or AGND, or to an output from the previous stage. The latter switches are not shown in
FIGS. 1A and 1B
for clarity. The non-overlapping clock signals in
FIG. 1C
control this two phase operation. During the first clock phase, Phase 1, the clock signal qs is high. The clock signal qg is high in the second clock phase, Phase 2. The clock signal qsp controls the sampling switch SW, and is identical to clock signal qs except that it has a preceding falling edge. In Phase 1, the bottom plates of the capacitor array are driven to the voltages at either of terminals Vref or AGND in accordance to the digital input j. At the same time, OTA is configured to be a unity gain buffer, and the bottom plate of capacitor Cf connects to terminal AGND. At the end of Phase 1, the sampling switch SW opens and traps the charge on the common top plate of all the capacitors. In Phase 2, the bottom plates of the capacitor array are driven according to the digital input j+1. The feedback capacitor Cf is connected between the output and the negative input of the OTA, thereby closing the loop. The output of OTA at the end of Phase 2 would ideally be equal to Vref/2. Any deviation from this ideal voltage is an error voltage, or DLE, associated with the code transition between code j and j+1. The error voltage is digitized by the subsequent stages of the ADC. This sequence is repeated for every code increment, and the results are incrementally accumulated in digital domain to derive the digital representation of ILE for all codes of the MDAC. The accumulation of code transition errors in digital domain by definition accumulates the digital truncation errors of all code transition errors.
U.S. Pat. No. 5,870,041 to Lee et al. recognizes this digital truncation error problem and attempts to reduce the truncation error just by increasing resolution of the over-all ADC used during error detection. This approach is common to minimizing truncation errors in general, but it does not solve the fundamental problem of truncation error limitations that stem from the error detection algorithm originally proposed in the above-cited paper authored by Lee et al. It also requires that all analog signals must settle to a higher resolution level with a small lsb size, which limits the maximum speed attainable for a given technology and power consumption.
Another practical limitation of the prior art circuits of
FIGS. 1A and 1B
is that the voltage reference, Vref changes between the two clock phases, due to its finite output impedance, thus limiting its capability to absorb switching transients and maintain the output voltage. This limitation becomes more pronounced for higher resolution, higher speed ADCs.
It would therefore be advantageous to provide a digital domain error detection and calibration algorithm for a multi stage pipeline ADC that is free from accumulation of digital truncation errors to thereby provide a multi stage pipeline ADC of inherently higher accuracy.
It would also be advantageous to provide a digital domain error detection method which exhibits greatly reduced sensitivity to changes in the reference voltage from one phase of operation to the other.
It would be further advantageous to provide a multi-stage pipeline ADC architecture that incorporates digital circuitry to perform the aforementioned digital domain error detection and calibration algorithm.
It would be further advantageous to provide a high speed, high resolution multi-stage pipeline ADC which offers superior performance with respect to accuracy, linearity, offset, gain error, total harmonic distortion (THD), spurious free dynamic range (SFDR), signal to noise ratio (SNR), and effective number of bits (ENOBs).
It would also be advantageous to provide a complementary metal oxide semiconductor process for implementing a multi stage pipeline ADC.
REFERENCES:
patent: 4903026 (1990-02-01), Tiemann et al.
patent: 5043732 (1991-08-01), Robertson et al.
patent: 5047772 (1991-09-01), Ribner
patent: 5274377 (1993-12-01), Masuura et al.
patent: 5465092 (1995-11-01), Mayes et al.
patent: 5499027 (1996-03-01), Karanicolas et al.
patent: 5510789 (1996-04-01), Lee
patent: 5635937 (1997-06-01), Lim et al.
patent: 5870041 (1999-02-01), Lee et al.
patent: 6348888 (2002-02-01), Yu
patent: 2001/0052869 (2001-12-01), Singer et al.
Lee et al., “Digital-Domain Calibration of Multistep Analog-to-Digital Converters,” IEEE Journal of Solid-State Circuits, vol. 27, No. 12, Dec., 1992, pp. 1679-1688.
Cline, “A Power Optimized 13-b 5 Msamples/s Pipelined Analog-to-Digital Converter in 1.2um CMOS,” IEEE Journal of Solid-State Circuits, vol. 31, No. 3, Mar., 1996 pp. 294-303.
Fairchild Semiconductor Corporation
Hein William E.
Nguyen John B
Young Brian
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