Pipeline analog to digital converter

Details Pipeline analog to digital converter Pipeline analog to digital converter

2003-12-16

2004-10-12

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000

Reexamination Certificate

active

06803873

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a pipeline analog-to-digital converter comprising a plurality of analog-to-digital converters, each for 1.5 bits (hereinafter referred to as an ADC), connected in series.
BACKGROUND OF THE INVENTION
FIGS. 1
to
3
are block diagrams broadly showing a conventional pipeline ADC, respectively.
As shown in
FIG. 1
illustrating a general configuration, this pipeline ADC has a sample-hold-amplifier (hereinafter referred to as an SHA) for sampling and holding an analog input signal A
1
in a predetermined cycle on the basis of a timing signal TM. Series-connected analog-to-digital conversion stages each for 1.5 bits (hereinafter referred to as an STG), namely, STGs
2
1
to
2
m
are connected to the output side of the SHA
1
.
The respective STGs
2
1
to
2
m
, as shown in
FIG. 2
illustrating the configuration thereof, comprise a sub-ADC ((hereinafter referred to as an SADC)
3
, a sub-digital-to-analog converter ((hereinafter referred to as an SDAC)
4
, a subtracter
5
, and an SHA
6
with a voltage amplification factor set at 2. The SADC
3
is for comparing an input voltage. V
1
with reference voltages ±VR/4, and detecting which of three voltage ranges, namely, a voltage range below −VR/4, a voltage range of from −VR/4 to +VR/4, and a voltage range above +VR/4, the input voltage V
1
falls in. Respective signals A, B, C, of 1.5 bits, indicating the result of such detection, are delivered to the SDAC
4
. The SDAC
4
outputs voltages −VR/2, 0, +VR/2 in accordance with the signals A, B, C, respectively. The output side of the SDAC
4
is connected to the negative input terminal of the subtracter
5
, and the input voltage V
1
is connected to the positive input terminal of the subtracter
5
. The subtracter
5
is for subtracting an output voltage of the SDAC
4
from the input voltage V
1
to thereby deliver a difference in voltage to the SHA
6
.
The SHA
6
amplifies the difference in voltage, delivered from the subtracter
5
, by a factor of two, and holds an amplified voltage, thereby outputting the amplified voltage as an output voltage VO.
Connected to the output side of the STG
2
m
in the final stage is an SADC
7
for converting a voltage outputted from the STG
2
m
into a digital signal of 2 bits. The signals A, B, C, representing the result of the detection by the respective STGs
2
1
to
2
m
, and the digital signal D outputted from the SADC
7
after conversion are delivered to an encoder
8
. Further, the timing signal TM generated by a timing generator
9
is delivered to the SHA
1
, the STGs
2
1
to
2
m
, the SADC
7
, and the encoder
8
.
The encoder
8
sequentially shifts and holds the signals A, B, C, representing the result of the detection, outputted from the respective STGs
2
1
to
2
m
, on the basis of the timing signal TM, executing pipeline processing of the respective detection results of the STGs
2
1
to
2
m
against the analog input signal A
1
, correspondingly to the digital signal D outputted from the SADC
7
, to thereby generate and output a digital signal DO.
FIG. 3
is an input/output characteristic diagram showing operation of the respective STGs
2
1
to
2
m
. The operation thereof is described hereinafter with reference to FIG.
3
.
The analog input signal A
1
is sampled on the basis of the timing signal TM, and held by the SHA
1
. The signal as held is delivered as the input voltage V
1
to the STGs
2
1
in the initial stage, whereupon the SADC
3
of the STGs
2
1
compares the input voltage V
1
with the reference voltages ±VR/4, to thereby make determination. The result of the determination is outputted by rendering any one of the signals A, B, C to represent “1”.
If the input voltage V
1
is below −VR/4, the signal A representing the result of the determination by the SADC
3
is turned into “1” while the signals B, C are turned into “0”, respectively. If the input voltage V
1
is in the range of from −VR/4 to +VR/4, the signal B is turned into “1” while the signals A, C are turned into “0”, respectively, and if the input voltage V
1
is above +VR/4, the signals A, B are turned into “0”, respectively, while the signal C is turned into “1”. Those signals A, B, C are delivered to the SDAC
4
.
At the SDAC
4
, when the signal A is “1”, −VR/2 is outputted as the reference voltage, and when the signals B, C are “1”, respectively, 0, +VR/2 are outputted as the reference voltages, respectively. The reference voltage outputted from the SDAC
4
is delivered to the subtracter
5
where the reference voltage is subtracted from the input voltage V
1
. A voltage outputted from the subtracter
5
is held by the SHA
6
on the basis of the timing signal TM and amplified by a factor of two before being delivered as the output voltage VO.
Thus, as shown in
FIG. 3
, if the input voltage V
1
of the STG
2
1
is in the voltage range below −VR/4, the output voltage VO thereof falls in a voltage range of from −VR to +VR/2. Further, if the input voltage V
1
is in the voltage range of from −VR/4 to +VR/4, the output voltage VO thereof falls in a voltage range of from −VR/2 to +VR/2, and if the input voltage V
1
is in the voltage range above +VR/4, the output voltage VO falls in a voltage range of from −VR/2 to +VR. The output voltage VO of the STG
2
1
is delivered as an input voltage V
1
to STG
2
2
in the next stage.
In this way, the respective digital signals of 1.5 bits are outputted from the respective STGs
2
1
to
2
m
, on the basis of the timing signal TM, and pipeline processing of those digital signals is executed by the encoder
8
, thereby generating the digital signal DO of a predetermined bits.
With the conventional pipeline ADC, however, the following problems have been encountered. That is, since the output voltage VO of each of the STGs
2
is delivered as an input voltage V
1
to the STG
2
in the next stage, strict linearity is required of the SHA
6
of the respective STGs
2
such that the output voltage is directly proportional to the input voltage. This is because in the case of poor linearity, an accurate digital value cannot be obtained due to nonlinear distortion at the time of amplification.
Meanwhile, the output voltage VO outputted from the respective STGs
2
1
to
2
m
ranges from −VR to +VR, and the input voltage to the SHA
6
, corresponding thereto, ranges from −VR/2 to +VR/2. Accordingly, accurate linearity against a wide range of the input voltage is required of the respective SHAs
6
. Furthermore, a higher conversion speed is required of the respective SHAs
6
. However, high accuracy and high speed being factors required of an amplifier, contradictory to each other, it is not possible to maximize both the factors at the same time. For this reason, with the conventional configuration as shown in
FIG. 1
, it has been impossible to provide the pipeline ADC simultaneously meeting requirements for high accuracy and high speed.
SUMMARY OF THE INVENTION
To solve the problems described as above, in accordance with a first aspect of the invention, there is provided a pipeline ADC for obtaining a digital output signal of a predetermined bits, corresponding to an analog input signal as the target for conversion, by executing pipeline processing based on a clock signal, said pipeline analog-to-digital converter comprising a plurality of STGs connected in series, each comprising an SADC for converting an analog input voltage into a digital signal of 1.5 bits, an SDAC for converting the digital signal into an analog voltage, and an amplifier for sampling and holding a difference in voltage between the input voltage and the analog voltage and amplifying the difference in voltage as held, wherein the STG to which the analog input signal is delivered, in the initial stage of said plurality of the STGs, has the following configuration.
That is, the STG in the initial stage comprises a first amplif

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