Pipeline ADC with minimum overhead digital error correction

Details Pipeline ADC with minimum overhead digital error correction Pipeline ADC with minimum overhead digital error correction

2007-10-09

2007-10-09

Nguyen, Linh (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S120000, C341S161000

Reexamination Certificate

active

11308119

ABSTRACT:
The most hardware efficient way to implement an N-stage pipeline ADC is to use (G+1)-level ADC-DAC for its first (N−1) stages and use (2·G−1)-level ADC for the last stage, where G is the inter-stage gain. For the fist (N−1) stages using (G+1)-level ADC-DAC, the (G+1) levels are uniformly distributed between −(G−1)/G and (G−1)/G; inclusively. The spacing between two adjacent levels is 2(G−1)/G2. For the last stage using (2·G−1)-level ADC, the (2·G−1)-levels are uniformly distributed between −(G−1)/G and (G−1)/G, inclusively. The spacing between two adjacent levels is 1/G.

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