Pipeline ADC with memory effects achieving one cycle...

Details Pipeline ADC with memory effects achieving one cycle... Pipeline ADC with memory effects achieving one cycle...

2007-02-21

2008-05-13

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000

Reexamination Certificate

active

07372391

ABSTRACT:
A data conversion stage circuit (104) for an opamp-shared pipeline analog-to-digital converter (ADC) (100) includes an over-range detection and recovery circuit including first and second switches (S3, S4) connected between respective input terminals (136, 137) and output terminals (138, 139) of the opamp (128) and both controlled by a first control signal, and a logic circuit (150) coupled to receive the first residue value and compare the first residue value to a pair of high and low comparison voltage levels. The logic circuit asserts the first control signal during a first clock phase when the first residue value is either greater than the high comparison voltage level or less than the low comparison voltage level. The high and low comparison voltage levels define a voltage region outside of a reference voltage range of the data conversion stage circuit where the reference voltage range defines in-range voltage values for the data conversion stage circuit.

REFERENCES:
patent: 6624698 (2003-09-01), Nagaraj
patent: 6731155 (2004-05-01), Hakkarainen et al.
patent: 6784824 (2004-08-01), Quinn
patent: 6967509 (2005-11-01), Rossi
patent: 7304598 (2007-12-01), Bogner et al.
patent: 2003/0151430 (2003-08-01), Hakkarainen et al.

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