Pipeline ADC using multiplying DAC and analog delay circuits

Details Pipeline ADC using multiplying DAC and analog delay circuits Pipeline ADC using multiplying DAC and analog delay circuits

2007-03-06

2007-03-06

Nguyen, Linh (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000, C341S122000

Reexamination Certificate

active

11198970

ABSTRACT:
Each stage of a pipeline ADC includes an analog delay cell, a sub-stage ADC, and a multiplying digital-to-analog converter (MDAC). The MDAC includes a sample-and-hold amplifier (SHA) circuit, a summer, a gain stage, and a DAC. The MDAC is arranged in cooperation with the analog delay cell such that the effects of a long comparator decision time under high-speed conditions are minimized. The first SHA, half clock cycle delay cell with unity gain transfer function, samples the input signal during the first clock period, followed by a strobe of the sub-ADC. Substantially half of the clock period can be utilized for the comparison time of the sub-ADC using the described methods. Since decoding is completed before MDAC sampling the first SHA output so that the complete half clock cycle can be arranged for amplifier settling in order to achieve the maximum operating speed with a given amplifier bandwidth.

REFERENCES:
patent: 5635937 (1997-06-01), Lim et al.
patent: 5677692 (1997-10-01), Hasegawa
patent: 6337651 (2002-01-01), Chiang
patent: 6486807 (2002-11-01), Jonsson
patent: 6501411 (2002-12-01), Soundarapandian et al.
patent: 6515606 (2003-02-01), Lyden
patent: 6710735 (2004-03-01), Lin
patent: 6756929 (2004-06-01), Ali
patent: 6801151 (2004-10-01), Opris
patent: 6822598 (2004-11-01), Kobayashi
patent: 6822601 (2004-11-01), Liu et al.
patent: 6839009 (2005-01-01), Ali
patent: 6861969 (2005-03-01), Ali
patent: 6963300 (2005-11-01), Lee
patent: 7002504 (2006-02-01), McMahill
patent: 7002506 (2006-02-01), Tadeparthy et al.
patent: 7009548 (2006-03-01), Chiang et al.
patent: 7084792 (2006-08-01), Hsu
patent: 7088278 (2006-08-01), Kurose et al.
Yang et al., “A 3-V 340mW 14-b 75-Msample/s CMOS ADC With 85-dB SFDR at Nyquist Input,”IEEE, Dec. 2001 (6 pgs.) no date.
Min et al., “A 69mW 10b 80MS/s Pipelined CMOS ADC,”IEEE, Feb. 12, 2003 (8 pgs.).
Limotyrakis et al., “A 150MS/s 8b 71mW Time-Interleaved ADC in 0.18μm CMOS,”IEEE, Feb. 17, 2004 (5 pgs.).
Stroeble et al., “An 80MHz 10b Pipeline ADC with Dynamic Range Doubling and Dynamic Reference Selection,”IEEE, Feb. 18, 2004 (3 pgs.).

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