Electrical pulse counters – pulse dividers – or shift registers: c – Applications – Including memory
Reexamination Certificate
1999-12-22
2001-04-10
Lam, Tuan T. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Applications
Including memory
C365S236000
Reexamination Certificate
active
06215837
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of inputting and outputting a plurality of data within one period of a clock.
DESCRIPTION OF THE PRIOR ART
With the increase of data output bandwidth in semiconductor memory devices, the DDR (Double Data Rate) method of outputting double data at rising and falling edges of a clock signal has been required instead of the SDR (Single Data Rate) method of outputting data only at a rising edge. In implementing data input/output circuits in the DDR method, it is very difficult to double the operation speed in a memory core because the memory core does not have an operation timing margin enough. Accordingly, it is inevitable to take such a double data input/output in a two-bit prefetch method. Generally, the operation speed of the memory core in the two-bit prefetch method is the same as that in the SDR (Single Data Rate) method, but the two-bit prefetch method in such as a DDR method puts double data in a latch circuit, which is in the front of a pipe counter, and processes each data at the rising and falling edges of a clock signal from the pipe counter. In other words, when the data stored in memory cells are read out, the pipe counter determines the order of the data output before outputting the data through an output buffer.
FIG. 1
is a schematic diagram illustrating the conventional SDR SDRAM device. As shown in
FIG. 1
, the conventional SDR SDRAM device includes a cell array block
10
, an NMOS transistor
11
, a sense amplifier
12
, a command decoder
13
, a pipe counter
14
, a pipe del signal generator
15
, a pipeline latch circuit
16
and an output driver
17
. In similar to typical DRAM devices, the NMOS transistor
111
transfers the data stored in the cell array block
10
to a pair of data bus lines db and dbb according to a bit line selection signal Yi, and the sense amplifier
12
amplifies the difference between the voltages on the data bus lines db and dbb and sends the amplified voltage difference through a global input/output line gio to the pipe del signal generator
15
and the pipeline latch circuit
16
. The command decoder
13
produces instructions for a read operation and the pipeline latch circuit
16
stores the transferred data from the sense amplifier
12
. The pipe counter
14
receives a read command from the command decoder
13
, an internal rising clock signal rclk, a CAS latency signal c
12
indicating that the CAS latency is of
2
, an output enable signal outen determining an output enable section in response to the read command and the CAS latency signal and a counter reset signal rst_pcnt_b to reset the pipeline latch circuit
16
, thereby producing a pipe counter signal pcnt for outputting, in this order, the data stored in the pipeline latch circuit
16
in response to the internal rising clock signal rclk. The pipe del signal generator
15
senses data on the global input/output line gio and produces a pipe del signal notifying the pipeline latch circuit
16
that data exist on the global input/output line gio. The output driver
17
receives an output from the pipeline latch circuit
16
and then buffers the final data output.
As stated above, in the conventional SDR SDRAM device, the data output is synchronized only with the rising edge of the clock signal (i.e., internal rising clock signal rclk) and the pipeline latch circuit
16
stores the data through only one global input/output line gio. Particularly, to increase the operation speed of the SDRAM device employing the SDR method, the external clock speed should be increased. However, the increase of the external clock speed requires an increase of the operation speed of other devices in a system as well as the memory devices. Accordingly, speeding up the external clock signal may cause many problems in a system. Also, since current clock frequency is more than 100 MHz, the period may be in at most 10 nsec. In the conventional SDR SDRAM device, it is very difficult to process two subsequent data during this short period. In case where the pipe counter of the SDR SDRAM device, which performs the data output operation to be synchronized with an external clock signal, is employed in the DDR SDRAM device, it is necessary to provide a complicated pipe counter making different reset signals associated with an operation mode of the SDR SDRAM device. Furthermore, it is impossible to apply the pipe counter of the SDR SDRAM device to the DDR SDRAM device because it is required to make pipeline counter signals for controlling pipeline latch circuits at another edge of the clock signal. As a result, it is impossible to adapt the conventional SDR SDRAM device to a basic model of the DDR SDRAM device.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a DDR SDRAM device having an improved pipe counter.
It is another abject of the present invention to provide a pipe counter for a DDR SDRAM device, by simply modifying a pipe counter for an SDR SDRAM device.
In accordance with another aspect of the present invention, there is provided a pipe counter comprising in a DDR SDRAM device, the pipe counter comprising: a controller for producing a counter control signal in response to rising and falling edge signals of an external clock signal; an enabling unit for producing a plurality of enable signals in response to the counter control signal and for enabling one of the enable signals during one period of the counter control signal; and a driver for receiving one of the enable signals, producing first and second pipe counter signals being synchronized with the rising and falling edge signals of the external clock signal, wherein one of the first and second pipe counter signals is activated during one period of the received enable signal.
REFERENCES:
patent: 6026054 (2000-02-01), Lee
patent: 6147926 (2000-11-01), Park
Hyundai Electronics Industries Co,. Ltd.
Jacobson Price Holman & Stern PLLC
Lam Tuan T.
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