Ping-pong amplifier with auto-zeroing and chopping

Amplifiers – With periodic switching input-output

Reexamination Certificate

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C330S051000, C327S124000

Reexamination Certificate

active

06476671

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of ping-pong amplifiers, and particularly to techniques for reducing low frequency noise and offset voltage errors for such amplifiers.
2. Description of the Related Art
Ping-pong amplifiers are well known and widely used due to their low input offset voltages. A schematic diagram of a basic ping-pong amplifier
10
is shown in FIG.
1
. Two gain amplifiers A
1
and A
2
, each of which has differential inputs and outputs, receive a differential input signal made up of signals INP and INN. The ping-pong amplifier also typically includes an output amplifier A
0
, which is connectable to the outputs of A
1
via a pair of switches S
1
and S
2
, or to the outputs of A
2
via a pair of switches S
3
and S
4
.
A pair of fully differential nulling amplifiers A
3
and A
4
are used to auto-zero A
1
and A
2
, respectively; the inputs of A
3
and A
4
are connected to the outputs of A
1
and A
2
via pairs of switches S
5
/S
6
, and S
7
/S
8
. A pair of memory capacitors C
1
and C
2
are connected to the inputs of A
3
, and capacitors C
3
and C
4
are connected to A
4
's inputs. A switch S
9
is connected between the inputs of A
1
, and a switch S
10
is connected between the inputs of A
2
. A switch S
11
is connected between the differential input signal and one of A
1
's inputs, and a switch S
12
is connected between the differential input signal and one of A
2
's inputs.
The switches are controlled with a control circuit (not shown), which operates them in accordance with the timing diagram shown in
FIG. 1
a.
The ping-pong amplifier has a two-phase timing cycle. During the first phase (&phgr;1), switches S
5
, S
6
and S
9
are closed, such that amplifier A
1
is auto-zeroed by the output currents of nulling amplifier A
3
, with the error signals stored on memory capacitors C
1
and C
2
. Switches S
3
, S
4
and S
12
are also closed, allowing the differential input signal to be amplified by A
2
followed by A
0
. The roles are reversed during the second phase (&phgr;2): switches S
7
, S
8
and S
10
are closed such that A
2
is auto-zeroed by A
4
(with the error signals stored on memory capacitors C
3
and C
4
), and switches S
1
, S
2
and S
11
are closed such that the input signal is amplified by A
1
followed by A
0
.
Auto-zeroing is effective in reducing offset voltage and
1
/f noise. However, the technique suffers from aliasing of wideband noise into the frequency range between DC and the auto-zeroing frequency. Because of this, the low frequency noise spectral density of a conventional auto-zeroed amplifier is several times higher than the thermal noise of a conventional CMOS op amp.
Some amplifiers seek to reduce offset voltage and
1
/f noise by “chopping” the input and output of the amplifier; i.e., modulating a low frequency input signal up to near a chopping frequency, where it is amplified and modulated back down to the original frequency. This technique does not suffer from wideband noise aliasing. However, chopping also modulates the offset voltage up to the chopping frequency, resulting in a large energy at the chopping frequency. This energy limits the usable bandwidth, and often requires filtering.
SUMMARY OF THE INVENTION
A ping-pong amplifier and method are presented which overcome the problems noted above. The invention employs auto-zeroing and chopping to simultaneously achieve low offset voltage and low low frequency noise, as well as low energy at the chopping frequency.
The novel ping-pong amplifier includes respective nulling amplifiers for each of its gain amplifiers, which auto-zero each gain amplifier. In addition, switches are included which allow the differential inputs and outputs of the gain amplifiers to be chopped. Thus, while one gain amplifier is being auto-zeroed, the other gain amplifier amplifies the input signal while its inputs and outputs are chopped.
One of the described embodiments includes circuitry which reduces switching transients that might otherwise appear in the amplifier's output. Here, each of gain amplifiers A
1
and A
2
includes a common-mode reference voltage input CMR connected to receive a common-mode reference voltage VCMR, and a common-mode feedback circuit; VCMR is typically set to a value between the amplifier's power rails so that the amplifier may have a high gain. The common-mode feedback circuit sets the amplifier's common-mode output voltage —given by the sum of its differential outputs divided by 2—so that each of its outputs is nominally set to VCMR when the differential output voltage is zero. The ping-pong amplifier includes an error amplifier, which has one input connected to common-mode reference voltage VCMR, its other input switchably connected to the common-mode output of one of the two gain amplifiers A
1
and A
2
, and an output which is switchably connected to the CMR inputs of A
1
and A
2
. Respective memory capacitors are connected to the two CMR inputs. In operation, the error amplifier's input is periodically connected to the common-mode output of A
1
, and its output is connected to A
1
's CMR input. This arrangement forms a closed-loop which forces A
1
's common-mode output voltage (referred to herein as “VCMR
1
”) to be equal to VCMR; the error amplifier's output voltage is stored on the memory capacitor connected to A
1
's CMR input. Similarly, the error amplifier's input and output are periodically connected to A
2
's common-mode output and CMR input, respectively, to force A
2
's common-mode output voltage (referred to herein as “VCMR2”) to be equal to VCMR, with the error amplifier's output voltage stored on the memory capacitor connected to the A
2
's CMR input. The voltages stored on the memory capacitors continuously adjust the common-mode output voltages so that VCMR1 and VCMR2 are held equal to VCMR. Keeping VCMR1=VCMR2=VCMR ensures that transients due to mismatch in the common-mode feedback circuit are largely reduced.
Further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings.


REFERENCES:
patent: 4931745 (1990-06-01), Goff et al.
patent: 5115202 (1992-05-01), Brown
patent: 6121831 (2000-09-01), Mack
patent: 6140872 (2000-10-01), McEldowney
patent: 6407630 (2002-06-01), Yao et al.
IEEE Journal of Solid-State Circuits, A Rail-to-Rail Ping-Pong Op-Amp, Ion E. Opris and Gregory T.A. Kovacs, vol. 31, No. 9, Sep. 1996, pp. 1320-1324.
Electronics, Chopper-Stabilized Op Amp Combines MOS and Bipolar Elements on One Chip, Sep. 27, 1973, pp. 209-213.
IEEE Journal of Solid-State Circuits, A Low-Noise Chopper-Stabilized Differential Switched-Capacitor Filtering Technique, vol. SC-16, No. 6, Dec. 1981, pp. 708-715.
IEE Journal of Solid-State Circuits, A Low Drift Fully Integrated MOSFET Operational Amplifier, vol. Sc-13, No. 4, Aug. 1978, pp. 499-503.

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