Pincer movement delay circuit for producing output signal...

Details Pincer movement delay circuit for producing output signal... Pincer movement delay circuit for producing output signal...

1998-04-06

2001-01-23

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S261000, C327S117000

Reexamination Certificate

active

06177823

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a delay circuit and, more particularly, to a pincer movement delay circuit for producing an output signal different in pulse repetition period from an input signal.
DESCRIPTION OF THE RELATED ART
The present inventor proposed a synchronous delay circuit in Japanese Patent Publication of Unexamined Application (JPA) No. 8-237091. The prior art synchronous delay circuit produces a timing signal at a half of clock repetition period of a clock signal.
FIG. 1
illustrates the prior art delay circuit already proposed by the present inventor.
The delay circuit comprises a first delay line
1
, a second delay line
2
and a transfer circuit
3
connected between the first delay line
1
and the second delay line
2
. The first delay line
1
is implemented by a series of delay elements, and the second delay line
2
is implemented by two series combination of delay elements. The transfer circuit
3
includes transfer gates arranged in parallel. The transfer gates have respective input nodes connected to the delay elements of the first delay line I and respective output nodes selectively connected to the delay elements of the two series combinations.
A clock signal CLK
1
is supplied from an input terminal
4
to a signal receiving circuit
5
, and the signal receiving circuit
5
produces a clock signal CLK
2
from the clock signal CLK
1
. The clock signal CLK
2
is directly supplied to the transfer circuit
3
as a control signal CTL
1
, and is supplied through a delay circuit
6
to the first delay line
1
.
The first delay line
1
rightwardly propagates the clock signal CLK
2
through the delay elements. The transfer circuit
3
is responsive to the control signal CTL
1
so as to selectively transfer a group of clock signals CLK
2
from the delay elements of the first delay line
1
to the delay elements of the second delay line
2
. The second delay line
2
leftwardly propagates the group of clock signals CLK
2
through the delay elements, and an OR gate
7
produces an output clock signal CLK
3
from the group of clock signals CLK
2
.
The second delay line
2
is designed to introduce delay half as long as the delay introduced by the first delay line
1
. Each clock pulse CLK
2
proceeds to a certain point of the first delay line
1
during the clock repetition period, and the next clock pulse CLK
2
causes the transfer circuit
3
to transfer the clock pulse CLK
2
to one of the two series combinations of the second delay line
2
. Then, the clock pulse CLK
2
is output from the second delay line
2
at the mid timing of the clock period. For this reason, the prior art delay circuit requires the first delay line
1
and the second delay line
2
exactly designed to introduce the two kinds of delay, and the Japanese Patent Publication of Unexamined Application proposes to regulate the number of the delay elements to 2:1. In other words, the output timing of the clock signal CLK
3
is dependent on the circuit configuration of the first and second delay lines
1
and
2
. However, even if the delay elements are selected to 2:1, the layout of the delay lines ½ are not taken into account, and a certain layout does not make the two kinds of delay time 2:1. This means that the output timing of the clock signal CLK
3
is offset from the mid point of the clock repetition period.
SUMMARY OF THE INVENTION
It is therefore an important object of the present invention to provide a delay circuit, which accurately produces an output pulse at a target timing.
In accordance with one aspect of the present invention, there is provided a delay circuit for producing an output timing signal from an input signal, and the delay circuit comprises a first delay line having a first node group implemented by a plurality of first nodes connected in series and propagating the input signal from an initial node of the first node group toward a final node of the first node group, a second delay line having a second node group implemented by a plurality of second nodes connected in series, propagating the input signal from an initial node of the second node group toward a final node of the second node group causing the initial node to the final node of the first node group to be respectively paired with the final node to the initial node of the second node group so as to form a plurality of node pairs and a comparator connected to the plurality of node pairs, and comparing outputs of the plurality of node pairs to see whether the outputs of any one of the plurality of node pairs are consistent with each other so as to determine a timing for producing the output timing signal.


REFERENCES:
patent: 5355037 (1994-10-01), Andresen
patent: 5430394 (1995-07-01), Mcminn
patent: 5475322 (1995-12-01), MacDonald
patent: 5528187 (1996-06-01), Sato et al.
patent: 5570294 (1996-10-01), Mcminn
patent: 5699003 (1997-12-01), Saeki
patent: 5712583 (1998-01-01), Frankeny
patent: 8-237091 (1996-09-01), None

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