Pin-scan-in type LSI logic circuit, pin-scan-in system driving c

Details Pin-scan-in type LSI logic circuit, pin-scan-in system driving c Pin-scan-in type LSI logic circuit, pin-scan-in system driving c

1993-06-04

1997-03-18

Ramirez, Ellis B.

Excavating

371 221, G01R 3128

Patent

active

056129629

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention relates to a pin-scan-in type LSI logic circuit which facilitates testing for short-circuits or wiring breaks in a circuit-mounting substrate in computers and the like. More specifically, the invention relates to a pin-scan-in system driving circuit for driving a pin-scan-in circuit provided in an LSI logic circuit as well as to a method of testing a substrate on which the LSI logic circuit is mounted.
A computer system on a network system such as a modern large-scale on-line system or a LAN affects the users quite seriously if it breaks down. A defective mounting substrate for the computers could become the cause of a breakdown. Therefore, any defective mounting substrate for the computers must be perfectly detected prior to shipping. The present invention is to provide an LSI logic circuit which makes it possible to perfectly and easily detect any defective mounting substrate for the computers, a method of driving such a circuit, and a method of testing such a circuit.


BACKGROUND OF THE INVENTION

In a mounting substrate used in modern computers mounting a number of LSIs very densely, the wiring patterns are so fine that defects such as short-circuits among the wirings or breaking of the wires are likely to easily develop.
The wiring test for such mounting substrates has, so far, simply consisted of checking the wire connection between points such as between output pins of the individual LSIs and input pins of other LSIs connected thereto, and checking the signal levels, but did not include checking for short-circuits and defects among the wirings. This is because the signal levels are quite different depending upon the output pins of the LSIs and it is difficult to determine abnormal conditions by specifying the levels produced by the wiring short-circuits. This will be described below with reference to a concrete example shown in FIG. 13, wherein reference numeral 1 denotes circuit-mounting substrates or LSI logic circuits mounting LSIA to LSIE, and reference numerals 1.sub.1 to 1.sub.6 denote wirings.
Here, for instance, a break in the wiring 1.sub.2 can be detected based on the fact that the output level of the LSIB to 1.sub.2 is not in agreement with the input level to the LSIE or that the input level of the LSIE fails to follow a change in the output level of the LSIB. Moreover, the short-circuit between 1.sub.4 and V.sub.EE can be detected based on the fact that the level of V.sub.EE becomes abnormal. However, the short-circuit or the defect between 1.sub.5 and 1.sub.6 cannot be detected when the 1.sub.5 output level of the LSIC and the 1.sub.6 output level of the LSID are both "1" or "0". Therefore, the logic outputs of the LSIs for 1.sub.5 and 1.sub.6 must be made different. That is, the short circuited condition is discriminated based on an intermediate level which is created by the combination of different levels of the two wirings. When there are a large number of wirings, therefore, there exist a tremendous number of combinations of the wirings that need checking for short-circuits, and it becomes very difficult to control the logic outputs.
The object of the present invention is to provide means which facilitates the detection of short-circuits among the wirings in testing the wirings of a substrate on which are mounted LSI logic circuits.


SUMMARY OF THE INVENTION

In order to achieve the above-mentioned object, the present invention basically employs the following technical constitution. That is, a first embodiment of the present invention is concerned with a pin-scan-in type LSI logic circuit comprising a pin-scan-in control means which has a plurality of input pins and output pins for outputting logic values, which selects any one output pin and forcibly renders it to assume a level of either a logic value 1 or a logic value 0, and which forcibly renders all other remaining output pins to assume the level of the other logic value. More concretely speaking, the first embodiment is concerned with the above-mentioned pin-scan-in type LSI logic circ

REFERENCES:
patent: 4972144 (1990-11-01), Lyon et al.
patent: 5056093 (1991-10-01), Whetsel
patent: 5101153 (1992-03-01), Morong, III
patent: 5303246 (1994-04-01), Anderson et al.

Affiliated with

Also associated with

Rating

Pin-scan-in type LSI logic circuit, pin-scan-in system driving c does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Pin-scan-in type LSI logic circuit, pin-scan-in system driving c, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pin-scan-in type LSI logic circuit, pin-scan-in system driving c will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1711600